Well-Posed Verilog-A Compact Model for Phase Change Memory

Shruti R. Kulkarni; Deepak Vinayak Kadetotad; Jae Sun Seo; Bipin Rajendran

doi:10.1109/SISPAD.2018.8551667

Well-Posed Verilog-A Compact Model for Phase Change Memory

Shruti R. Kulkarni, Deepak Vinayak Kadetotad, Jae Sun Seo, Bipin Rajendran

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

In this work, we demonstrate a well-posed compact model for phase change memory (PCM) devices based on Ge ₂ Sb ₂ Te ₅ , (GST) chalcogenide. This model supports all modes of simulation including transient, DC, and AC. The model is developed in Verilog-A and simulated using HSPICE. It is computationally simple and successfully captures the key high level behaviors of memory switching, including the resistance dependence on programming voltages, currents and pulse time-scales.

Original language	English
Title of host publication	SISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	369-373
Number of pages	5
ISBN (Electronic)	9781538667880
DOIs	https://doi.org/10.1109/SISPAD.2018.8551667
State	Published - Nov 28 2018
Externally published	Yes
Event	2018 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2018 - Austin, United States Duration: Sep 24 2018 → Sep 26 2018

Publication series

Name	International Conference on Simulation of Semiconductor Processes and Devices, SISPAD
Volume	2018-September

Conference

Conference	2018 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2018
Country/Territory	United States
City	Austin
Period	09/24/18 → 09/26/18

Funding

ACKNOWLEDGEMENTS This work was supported in part by the Semiconductor Research Corporation under grant number 2016-SD-2717, the CAMPUSENSE project grant from CISCO Systems Inc; and the National Science Foundation grant 1710009.

Keywords

Phase change memory
Verilog-A
chalcogenide
well-posed model

Access to Document

10.1109/SISPAD.2018.8551667

Cite this

Kulkarni, S. R., Kadetotad, D. V., Seo, J. S., & Rajendran, B. (2018). Well-Posed Verilog-A Compact Model for Phase Change Memory. In SISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings (pp. 369-373). Article 8551667 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD; Vol. 2018-September). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SISPAD.2018.8551667

Kulkarni, Shruti R. ; Kadetotad, Deepak Vinayak ; Seo, Jae Sun et al. / Well-Posed Verilog-A Compact Model for Phase Change Memory. SISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 369-373 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD).

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title = "Well-Posed Verilog-A Compact Model for Phase Change Memory",

abstract = " In this work, we demonstrate a well-posed compact model for phase change memory (PCM) devices based on Ge 2 Sb 2 Te 5 , (GST) chalcogenide. This model supports all modes of simulation including transient, DC, and AC. The model is developed in Verilog-A and simulated using HSPICE. It is computationally simple and successfully captures the key high level behaviors of memory switching, including the resistance dependence on programming voltages, currents and pulse time-scales.",

keywords = "Phase change memory, Verilog-A, chalcogenide, well-posed model",

author = "Kulkarni, \{Shruti R.\} and Kadetotad, \{Deepak Vinayak\} and Seo, \{Jae Sun\} and Bipin Rajendran",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2018 ; Conference date: 24-09-2018 Through 26-09-2018",

year = "2018",

month = nov,

day = "28",

doi = "10.1109/SISPAD.2018.8551667",

language = "English",

series = "International Conference on Simulation of Semiconductor Processes and Devices, SISPAD",

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Kulkarni, SR, Kadetotad, DV, Seo, JS & Rajendran, B 2018, Well-Posed Verilog-A Compact Model for Phase Change Memory. in SISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings., 8551667, International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, vol. 2018-September, Institute of Electrical and Electronics Engineers Inc., pp. 369-373, 2018 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2018, Austin, United States, 09/24/18. https://doi.org/10.1109/SISPAD.2018.8551667

Well-Posed Verilog-A Compact Model for Phase Change Memory. / Kulkarni, Shruti R.; Kadetotad, Deepak Vinayak; Seo, Jae Sun et al.
SISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2018. p. 369-373 8551667 (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD; Vol. 2018-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Rajendran, Bipin

PY - 2018/11/28

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AB - In this work, we demonstrate a well-posed compact model for phase change memory (PCM) devices based on Ge 2 Sb 2 Te 5 , (GST) chalcogenide. This model supports all modes of simulation including transient, DC, and AC. The model is developed in Verilog-A and simulated using HSPICE. It is computationally simple and successfully captures the key high level behaviors of memory switching, including the resistance dependence on programming voltages, currents and pulse time-scales.

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Kulkarni SR, Kadetotad DV, Seo JS, Rajendran B. Well-Posed Verilog-A Compact Model for Phase Change Memory. In SISPAD 2018 - 2018 International Conference on Simulation of Semiconductor Processes and Devices, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2018. p. 369-373. 8551667. (International Conference on Simulation of Semiconductor Processes and Devices, SISPAD). doi: 10.1109/SISPAD.2018.8551667

Well-Posed Verilog-A Compact Model for Phase Change Memory

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Keywords

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