Abstract
Because of increasing complexity in the memory hierarchy, predicting the performance of a given application in a given processor is becoming more difficult. The problem is worsened by the fact that the hardware needed to deal with more complex memory traffic also affects energy consumption. Moreover, in a heterogeneous system with shared main memory, the memory traffic between the last level cache (LLC) and the memory creates contention between other processors and accelerator devices. For these reasons, it is important to investigate and understand the impact of different memory access patterns on the memory system. This study investigates the interplay between Intel processors' memory hierarchy and different memory access patterns in applications. The authors explore sequential streaming and strided memory access patterns with the objective of predicting LLC-dynamic random access memory (DRAM) traffic for a given application in given Intel architectures. Moreover, the impact of prefetching is also investigated in this study. Experiments with different Intel micro-architectures uncover mechanisms to predict LLC-DRAM traffic that can yield up to 99% accuracy for sequential streaming access patterns and up to 95% accuracy for strided access patterns.
| Original language | English |
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| Title of host publication | Proceedings of MCHPC 2020 |
| Subtitle of host publication | Workshop on Memory Centric High Performance Computing, Held in conjunction with SC 2020: The International Conference for High Performance Computing, Networking, Storage and Analysis |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 52-61 |
| Number of pages | 10 |
| ISBN (Electronic) | 9781665422789 |
| DOIs | |
| State | Published - Nov 2020 |
| Event | 2020 IEEE/ACM Workshop on Memory Centric High Performance Computing, MCHPC 2020 - Virtual, Atlanta, United States Duration: Nov 11 2020 → … |
Publication series
| Name | Proceedings of MCHPC 2020: Workshop on Memory Centric High Performance Computing, Held in conjunction with SC 2020: The International Conference for High Performance Computing, Networking, Storage and Analysis |
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Conference
| Conference | 2020 IEEE/ACM Workshop on Memory Centric High Performance Computing, MCHPC 2020 |
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| Country/Territory | United States |
| City | Virtual, Atlanta |
| Period | 11/11/20 → … |
Funding
This manuscript has been co-authored by UT-Battelle, LLC under Contract No. DE-AC05-00OR22725 with the U.S. Department of Energy. The United States Government retains and the publisher, by accepting the article for publication, acknowledges that the United States Government retains a nonexclusive, paid-up, irrevocable, worldwide license to publish or reproduce the published form of this manuscript, or allow others to do so, for United States Government purposes. The Department of Energy will provide public access to these results of federally sponsored research in accordance with the DOE Public Access Plan. This research was supported in part by the following sources: Defense Advanced Research Projects Agency (DARPA) Microsystems Technology Office (MTO) Domain-Specific System-on-Chip Program and the US Department of Energy (DOE) Advanced Scientific Computing Research (ASCR) program.
Keywords
- Broadwell
- Cascade Lake
- Intel
- Sky Lake
- memory access patterns
- memory traffic prediction