TY - GEN
T1 - Understanding Performance Portability of SYCL Kernels
T2 - 2023 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2023
AU - Jin, Zheming
AU - Vetter, Jeffrey S.
N1 - Publisher Copyright:
© 2023 IEEE.
PY - 2023
Y1 - 2023
N2 - SYCL is a portable programming model. Toward the goal of a better understanding of performance portability of SYCL kernels on GPUs, we select a bioinformatics kernel for computing the all-pairs distance as a case study. After migrating the kernel from CUDA to HIP and SYCL, we evaluate the performance of the CUDA, HIP, and SYCL kernels on NVIDIA V100 and AMD MI210 GPUs. We analyze the GPU instructions from the kernels to explain performance gaps between SYCL and CUDA/HIP. We hope that the findings are valuable for improving performance portability of SYCL.
AB - SYCL is a portable programming model. Toward the goal of a better understanding of performance portability of SYCL kernels on GPUs, we select a bioinformatics kernel for computing the all-pairs distance as a case study. After migrating the kernel from CUDA to HIP and SYCL, we evaluate the performance of the CUDA, HIP, and SYCL kernels on NVIDIA V100 and AMD MI210 GPUs. We analyze the GPU instructions from the kernels to explain performance gaps between SYCL and CUDA/HIP. We hope that the findings are valuable for improving performance portability of SYCL.
KW - Heterogeneous computing
KW - Performance portabuity
KW - programming model
UR - http://www.scopus.com/inward/record.url?scp=85169292674&partnerID=8YFLogxK
U2 - 10.1109/IPDPSW59300.2023.00067
DO - 10.1109/IPDPSW59300.2023.00067
M3 - Conference contribution
AN - SCOPUS:85169292674
T3 - 2023 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2023
SP - 366
EP - 372
BT - 2023 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2023
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 15 May 2023 through 19 May 2023
ER -