Understanding and analyzing interconnect errors and network congestion on a large scale HPC system

Mohit Kumar; Saurabh Gupta; Tirthak Patel; Michael Wilder; Weisong Shi; Song Fu; Christian Engelmann; Devesh Tiwari

doi:10.1109/DSN.2018.00023

Understanding and analyzing interconnect errors and network congestion on a large scale HPC system

Mohit Kumar, Saurabh Gupta, Tirthak Patel, Michael Wilder, Weisong Shi, Song Fu, Christian Engelmann, Devesh Tiwari

Intelligent Systems and Facilities

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

11 Scopus citations

Abstract

Today's High Performance Computing (HPC) systems are capable of delivering performance in the order of petaflops due to the fast computing devices, network interconnect, and back-end storage systems. In particular, interconnect resilience and congestion resolution methods have a major impact on the overall interconnect and application performance. This is especially true for scientific applications running multiple processes on different compute nodes as they rely on fast network messages to communicate and synchronize frequently. Unfortunately, the HPC community lacks state-of-practice experience reports that detail how different interconnect errors and congestion events occur on large-scale HPC systems. Therefore, in this paper, we process and analyze interconnect data of the Titan supercomputer to develop a thorough understanding of interconnects faults, errors and congestion events. We also study the interaction between interconnect, errors, network congestion and application characteristics.

Original language	English
Title of host publication	Proceedings - 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	107-114
Number of pages	8
ISBN (Electronic)	9781538655955
DOIs	https://doi.org/10.1109/DSN.2018.00023
State	Published - Jul 19 2018
Event	48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2018 - Luxembourg City, Luxembourg Duration: Jun 25 2018 → Jun 28 2018

Publication series

Name	Proceedings - 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2018

Conference

Conference	48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2018
Country/Territory	Luxembourg
City	Luxembourg City
Period	06/25/18 → 06/28/18

Funding

This manuscript has been authored by UT-Battelle,LLC under Contract No. DE-AC05-00OR22725with the U.S. Department of Energy. The United States Government retains and the publisher, by accepting the article for publication, acknowledges that the United States Government retains a non-exclusive, paid-up, irrevocable, world-wide license to publish or reproduce the published form of this manuscript, or allow others to do so, for United States Government purposes. The Department of Energy will provide public access to these results of federally sponsored research in accordance with the DOE Public Access Plan (http://energy.gov/downloads/doe-public-access-plan).

Funders	Funder number
Office of AdvancedScientific Computing Research
National Science Foundation	1563750, 1561216, 1563728
U.S. Department of Energy	DE-AC05-00OR22725
Office of Science
North-Eastern Hill University

Keywords

Cray
Errors
Gemini
Interconnect
Titan

Access to Document

10.1109/DSN.2018.00023

Cite this

Kumar, M., Gupta, S., Patel, T., Wilder, M., Shi, W., Fu, S., Engelmann, C., & Tiwari, D. (2018). Understanding and analyzing interconnect errors and network congestion on a large scale HPC system. In Proceedings - 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2018 (pp. 107-114). Article 8416475 (Proceedings - 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DSN.2018.00023

Kumar, Mohit ; Gupta, Saurabh ; Patel, Tirthak et al. / Understanding and analyzing interconnect errors and network congestion on a large scale HPC system. Proceedings - 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2018. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 107-114 (Proceedings - 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2018).

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title = "Understanding and analyzing interconnect errors and network congestion on a large scale HPC system",

abstract = "Today's High Performance Computing (HPC) systems are capable of delivering performance in the order of petaflops due to the fast computing devices, network interconnect, and back-end storage systems. In particular, interconnect resilience and congestion resolution methods have a major impact on the overall interconnect and application performance. This is especially true for scientific applications running multiple processes on different compute nodes as they rely on fast network messages to communicate and synchronize frequently. Unfortunately, the HPC community lacks state-of-practice experience reports that detail how different interconnect errors and congestion events occur on large-scale HPC systems. Therefore, in this paper, we process and analyze interconnect data of the Titan supercomputer to develop a thorough understanding of interconnects faults, errors and congestion events. We also study the interaction between interconnect, errors, network congestion and application characteristics.",

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Kumar, M, Gupta, S, Patel, T, Wilder, M, Shi, W, Fu, S, Engelmann, C & Tiwari, D 2018, Understanding and analyzing interconnect errors and network congestion on a large scale HPC system. in Proceedings - 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2018., 8416475, Proceedings - 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2018, Institute of Electrical and Electronics Engineers Inc., pp. 107-114, 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2018, Luxembourg City, Luxembourg, 06/25/18. https://doi.org/10.1109/DSN.2018.00023

Understanding and analyzing interconnect errors and network congestion on a large scale HPC system. / Kumar, Mohit; Gupta, Saurabh; Patel, Tirthak et al.
Proceedings - 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2018. Institute of Electrical and Electronics Engineers Inc., 2018. p. 107-114 8416475 (Proceedings - 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Fu, Song

AU - Engelmann, Christian

AU - Tiwari, Devesh

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AB - Today's High Performance Computing (HPC) systems are capable of delivering performance in the order of petaflops due to the fast computing devices, network interconnect, and back-end storage systems. In particular, interconnect resilience and congestion resolution methods have a major impact on the overall interconnect and application performance. This is especially true for scientific applications running multiple processes on different compute nodes as they rely on fast network messages to communicate and synchronize frequently. Unfortunately, the HPC community lacks state-of-practice experience reports that detail how different interconnect errors and congestion events occur on large-scale HPC systems. Therefore, in this paper, we process and analyze interconnect data of the Titan supercomputer to develop a thorough understanding of interconnects faults, errors and congestion events. We also study the interaction between interconnect, errors, network congestion and application characteristics.

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Kumar M, Gupta S, Patel T, Wilder M, Shi W, Fu S et al. Understanding and analyzing interconnect errors and network congestion on a large scale HPC system. In Proceedings - 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2018. Institute of Electrical and Electronics Engineers Inc. 2018. p. 107-114. 8416475. (Proceedings - 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2018). doi: 10.1109/DSN.2018.00023

Understanding and analyzing interconnect errors and network congestion on a large scale HPC system

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Keywords

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