Towards numerical benchmark for half-precision floating point arithmetic

Piotr Luszczek; Jakub Kurzak; Ichitaro Yamazaki; Jack Dongarra

doi:10.1109/HPEC.2017.8091031

Towards numerical benchmark for half-precision floating point arithmetic

Piotr Luszczek, Jakub Kurzak, Ichitaro Yamazaki, Jack Dongarra

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

9 Scopus citations

Abstract

With NVIDA Tegra Jetson X1 and Pascal P100 GPUs, NVIDIA introduced hardware-based computation on FP16 numbers also called half-precision arithmetic. In this talk, we will introduce the steps required to build a viable benchmark for this new arithmetic format. This will include the connections to established IEEE floating point standards and existing HPC benchmarks. The discussion will focus on performance and numerical stability issues that are important for this kind of benchmarking and how they relate to NVIDIA platforms.

Original language	English
Title of host publication	2017 IEEE High Performance Extreme Computing Conference, HPEC 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538634721
DOIs	https://doi.org/10.1109/HPEC.2017.8091031
State	Published - Oct 30 2017
Externally published	Yes
Event	2017 IEEE High Performance Extreme Computing Conference, HPEC 2017 - Waltham, United States Duration: Sep 12 2017 → Sep 14 2017

Publication series

Name	2017 IEEE High Performance Extreme Computing Conference, HPEC 2017

Conference

Conference	2017 IEEE High Performance Extreme Computing Conference, HPEC 2017
Country/Territory	United States
City	Waltham
Period	09/12/17 → 09/14/17

Funding

This research was supported by the National Science Foundation through Award 1439052. Also, this research was supported by the Exascale Computing Project (17-SC-20-SC), a collaborative effort of the U.S. Department of Energy Office of Science and the National Nuclear Security Administration.

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10.1109/HPEC.2017.8091031

Cite this

Luszczek, P., Kurzak, J., Yamazaki, I., & Dongarra, J. (2017). Towards numerical benchmark for half-precision floating point arithmetic. In 2017 IEEE High Performance Extreme Computing Conference, HPEC 2017 Article 8091031 (2017 IEEE High Performance Extreme Computing Conference, HPEC 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/HPEC.2017.8091031

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Luszczek, P, Kurzak, J, Yamazaki, I & Dongarra, J 2017, Towards numerical benchmark for half-precision floating point arithmetic. in 2017 IEEE High Performance Extreme Computing Conference, HPEC 2017., 8091031, 2017 IEEE High Performance Extreme Computing Conference, HPEC 2017, Institute of Electrical and Electronics Engineers Inc., 2017 IEEE High Performance Extreme Computing Conference, HPEC 2017, Waltham, United States, 09/12/17. https://doi.org/10.1109/HPEC.2017.8091031

Towards numerical benchmark for half-precision floating point arithmetic. / Luszczek, Piotr; Kurzak, Jakub; Yamazaki, Ichitaro et al.
2017 IEEE High Performance Extreme Computing Conference, HPEC 2017. Institute of Electrical and Electronics Engineers Inc., 2017. 8091031 (2017 IEEE High Performance Extreme Computing Conference, HPEC 2017).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Towards numerical benchmark for half-precision floating point arithmetic

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