Towards an Integrated GPU Accelerated SoC as a Flight Computer for Small Satellites

Caleb Adams; Allen Spain; Jackson Parker; Matthew Hevert; James Roach; David Cotten

doi:10.1109/AERO.2019.8741765

Towards an Integrated GPU Accelerated SoC as a Flight Computer for Small Satellites

Caleb Adams
, Allen Spain
, Jackson Parker
, Matthew Hevert
, James Roach
, David Cotten

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

38 Scopus citations

Abstract

Many small satellites are designed to utilize cutting edge technology with the goal of rapidly advancing space based capabilities. As a result, many components take advantage of developments from the miniaturization of smartphone technology. Within the past 2 years, the UGA Small Satellite Research Laboratory has extended this concept into embedded GPUs for high-performance processing in LEO. Here we showcase advances in our research of high-performance space-based computation by integrating a traditional flight computer with existing miniaturized GPU/SoC systems. Such a system paves the way for many of NASA's goals that require space based AI, neural networks, computer vision, and high performance computing. Our system fits a standard CubeSat PC/104+ form factor, and implements many standard protocols such as I2C, SPI, UART, and RS422. The system also has several GPIO pins, 2 USB-C ports, a micro USB port for flashing, an Ethernet port, and a micro SD card slot for development. Additionally, the system is designed to be modular, so that GPU accelerated SoCs can be stacked to form a distributed system. For our primary computer, which handles I/O and initializes processes on the SoC, we choose to use the radiation tolerant Smart Fusion 2 SoC with an ARM Cortex-M3 processor and a FPGA. In addition to this primary computer, we use the Nvidia Tegra X2/X2i as the GPU/SoC workhorse. The primary computer and the TX2i are designed to share memory space with peripherals mounted onto the board, so that no significant file transfer is required between the subsystems. Additionally, Nvidia's Pascal architecture enables GPU-CPU or GPU-GPU communication without PCIe, enabling dense interconnected networks for monitoring and computation. To address thermal concerns, we cap the TX2i's power draw at 7.5 Watts, provide recommendations for thermal interface materials, and ensure that the primary computer only enables the GPU/SoC when parallel computation is specifically requested. Furthermore, radiation mitigation techniques are explored with ECC, software mitigation techniques, and aluminized kapton sheets. In conclusion, this system is a step towards a miniaturized high-performance flight computer well suited for future computational demands.

Original language	English
Title of host publication	2019 IEEE Aerospace Conference, AERO 2019
Publisher	IEEE Computer Society
ISBN (Electronic)	9781538668542
DOIs	https://doi.org/10.1109/AERO.2019.8741765
State	Published - Mar 2019
Externally published	Yes
Event	2019 IEEE Aerospace Conference, AERO 2019 - Big Sky, United States Duration: Mar 2 2019 → Mar 9 2019

Publication series

Name	IEEE Aerospace Conference Proceedings
Volume	2019-March
ISSN (Print)	1095-323X

Conference

Conference	2019 IEEE Aerospace Conference, AERO 2019
Country/Territory	United States
City	Big Sky
Period	03/2/19 → 03/9/19

Funding

The authors would like to thank the Georgia Space Grant Consortium for funding these GPU research projects and the Air Force Research Laboratory’s University Nanosat Program for giving us tremendous opportunities and for funding the projects that led us to this point. Additionally the authors would like to thank Erick Gavilanes for making the initial design for the CORGI in 2017 and getting us to a point where we could perform iterations and follow up research. Thanks to Casper Versteeg for providing significant knowledge and results relating thermal mitigation. Nir Patel, Nicholas Heavner, and Michael Buzzy did great work by contributing to the thermal models. A big thanks Justin Heimerl, for supplying CAD and working on electrical design and to Sydney Whilden and Adam King for doing initial radiation research and laying the foundations for this paper in that respect. A special thanks to Dr. Deepak Mishra for helping support the University of Georgia’s Small Satellite Research Laboratory from the beginning. Another thank you to Roger Hunter.

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10.1109/AERO.2019.8741765

Cite this

@inproceedings{9db1d2ac77024cab88151fe366cc2e90,

title = "Towards an Integrated GPU Accelerated SoC as a Flight Computer for Small Satellites",

abstract = "Many small satellites are designed to utilize cutting edge technology with the goal of rapidly advancing space based capabilities. As a result, many components take advantage of developments from the miniaturization of smartphone technology. Within the past 2 years, the UGA Small Satellite Research Laboratory has extended this concept into embedded GPUs for high-performance processing in LEO. Here we showcase advances in our research of high-performance space-based computation by integrating a traditional flight computer with existing miniaturized GPU/SoC systems. Such a system paves the way for many of NASA's goals that require space based AI, neural networks, computer vision, and high performance computing. Our system fits a standard CubeSat PC/104+ form factor, and implements many standard protocols such as I2C, SPI, UART, and RS422. The system also has several GPIO pins, 2 USB-C ports, a micro USB port for flashing, an Ethernet port, and a micro SD card slot for development. Additionally, the system is designed to be modular, so that GPU accelerated SoCs can be stacked to form a distributed system. For our primary computer, which handles I/O and initializes processes on the SoC, we choose to use the radiation tolerant Smart Fusion 2 SoC with an ARM Cortex-M3 processor and a FPGA. In addition to this primary computer, we use the Nvidia Tegra X2/X2i as the GPU/SoC workhorse. The primary computer and the TX2i are designed to share memory space with peripherals mounted onto the board, so that no significant file transfer is required between the subsystems. Additionally, Nvidia's Pascal architecture enables GPU-CPU or GPU-GPU communication without PCIe, enabling dense interconnected networks for monitoring and computation. To address thermal concerns, we cap the TX2i's power draw at 7.5 Watts, provide recommendations for thermal interface materials, and ensure that the primary computer only enables the GPU/SoC when parallel computation is specifically requested. Furthermore, radiation mitigation techniques are explored with ECC, software mitigation techniques, and aluminized kapton sheets. In conclusion, this system is a step towards a miniaturized high-performance flight computer well suited for future computational demands.",

author = "Caleb Adams and Allen Spain and Jackson Parker and Matthew Hevert and James Roach and David Cotten",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 2019 IEEE Aerospace Conference, AERO 2019 ; Conference date: 02-03-2019 Through 09-03-2019",

year = "2019",

month = mar,

doi = "10.1109/AERO.2019.8741765",

language = "English",

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Adams, C, Spain, A, Parker, J, Hevert, M, Roach, J & Cotten, D 2019, Towards an Integrated GPU Accelerated SoC as a Flight Computer for Small Satellites. in 2019 IEEE Aerospace Conference, AERO 2019., 8741765, IEEE Aerospace Conference Proceedings, vol. 2019-March, IEEE Computer Society, 2019 IEEE Aerospace Conference, AERO 2019, Big Sky, United States, 03/2/19. https://doi.org/10.1109/AERO.2019.8741765

Towards an Integrated GPU Accelerated SoC as a Flight Computer for Small Satellites. / Adams, Caleb; Spain, Allen; Parker, Jackson et al.
2019 IEEE Aerospace Conference, AERO 2019. IEEE Computer Society, 2019. 8741765 (IEEE Aerospace Conference Proceedings; Vol. 2019-March).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - Many small satellites are designed to utilize cutting edge technology with the goal of rapidly advancing space based capabilities. As a result, many components take advantage of developments from the miniaturization of smartphone technology. Within the past 2 years, the UGA Small Satellite Research Laboratory has extended this concept into embedded GPUs for high-performance processing in LEO. Here we showcase advances in our research of high-performance space-based computation by integrating a traditional flight computer with existing miniaturized GPU/SoC systems. Such a system paves the way for many of NASA's goals that require space based AI, neural networks, computer vision, and high performance computing. Our system fits a standard CubeSat PC/104+ form factor, and implements many standard protocols such as I2C, SPI, UART, and RS422. The system also has several GPIO pins, 2 USB-C ports, a micro USB port for flashing, an Ethernet port, and a micro SD card slot for development. Additionally, the system is designed to be modular, so that GPU accelerated SoCs can be stacked to form a distributed system. For our primary computer, which handles I/O and initializes processes on the SoC, we choose to use the radiation tolerant Smart Fusion 2 SoC with an ARM Cortex-M3 processor and a FPGA. In addition to this primary computer, we use the Nvidia Tegra X2/X2i as the GPU/SoC workhorse. The primary computer and the TX2i are designed to share memory space with peripherals mounted onto the board, so that no significant file transfer is required between the subsystems. Additionally, Nvidia's Pascal architecture enables GPU-CPU or GPU-GPU communication without PCIe, enabling dense interconnected networks for monitoring and computation. To address thermal concerns, we cap the TX2i's power draw at 7.5 Watts, provide recommendations for thermal interface materials, and ensure that the primary computer only enables the GPU/SoC when parallel computation is specifically requested. Furthermore, radiation mitigation techniques are explored with ECC, software mitigation techniques, and aluminized kapton sheets. In conclusion, this system is a step towards a miniaturized high-performance flight computer well suited for future computational demands.

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M3 - Conference contribution

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PB - IEEE Computer Society

T2 - 2019 IEEE Aerospace Conference, AERO 2019

Y2 - 2 March 2019 through 9 March 2019

ER -

Towards an Integrated GPU Accelerated SoC as a Flight Computer for Small Satellites

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