Abstract
In the framework of perfect loop nests with uniform dependences, tiling has been extensively studied as a source-to-source program transformation. Little work has been devoted to the mapping and scheduling of the tiles on to physical processors. We present several new results in the context of limited computational resources, and assuming communication-computation overlap. In particular, under some reasonable assumptions, we derive the optimal mapping and scheduling of tiles to physical processors.
| Original language | English |
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| Pages | 229-238 |
| Number of pages | 10 |
| State | Published - 1997 |
| Externally published | Yes |
| Event | Proceedings of the 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP'97 - Zurich, Switz Duration: Jul 14 1997 → Jul 16 1997 |
Conference
| Conference | Proceedings of the 1997 IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP'97 |
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| City | Zurich, Switz |
| Period | 07/14/97 → 07/16/97 |