The Fault in Our Chips: A Survey on Edge AI Accelerator Vulnerabilities

Edge AI accelerators, such as TPUs, NPUs, and custom low-power ASICs - are increasingly used in real-time, battery-operated systems for on-device deep learning. However, their deployment in resource-constrained and physically exposed environments raises serious concerns about hardware reliability and security. Faults in these systems can be transient (e.g., due to voltage fluctuations or radiation), permanent (e.g., aging or manufacturing defects), or even adversarially induced through targeted bit-flip attacks. This survey provides a comprehensive overview of hardware faults in AI accelerators, with a particular focus on edge deployment scenarios. We examine the fault models, detection and mitigation techniques, and unique challenges posed by limited on-chip resources and real-time constraints. Unlike prior surveys focusing mainly on random fault tolerance in general-purpose settings, our work highlights how faults at the edge can also be intentional attack vectors, blurring the line between reliability and security. The goal is to guide the development of resilient edge AI hardware capable of withstanding natural and malicious fault events.