Temperature-compensated reference circuits for SOI

  • S. C. Terry
  • , S. Chen
  • , B. J. Blalock
  • , J. R. Jackson
  • , B. M. Dufrene
  • , M. M. Mojarradi
  • , S. K. Islam
  • , M. N. Ericson

    Research output: Contribution to journalConference articlepeer-review

    13 Scopus citations

    Abstract

    Two novel reference circuits that exploit unique aspects of SOI technology are reported. The first is a voltage reference based on the G 4-FET, a new four-gate transistor possible only in SOI; which achieves a temperature-compensated output voltage without the use of the standard bandgap architecture. The second is a current reference that uses the zero leakage p-well resistor available in many SOI technologies to achieve a low-level, temperature-stable reference current that exceeds the specifications of bulk CMOS low-level current references reported in the literature. Both reference circuits have been implemented in a standard 3.3-V/0.35-μm partially depleted (PD)-SOI process.

    Original languageEnglish
    Article number5.2
    Pages (from-to)112-114
    Number of pages3
    JournalProceedings - IEEE International SOI Conference
    StatePublished - 2004
    Event2004 IEEE International SOI Conference, Proceedings - Charleston, SC, United States
    Duration: Oct 4 2004Oct 7 2004

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