Temperature-compensated reference circuits for SOI

S. C. Terry; S. Chen; B. J. Blalock; J. R. Jackson; B. M. Dufrene; M. M. Mojarradi; S. K. Islam; M. N. Ericson

Temperature-compensated reference circuits for SOI

S. C. Terry, S. Chen, B. J. Blalock, J. R. Jackson, B. M. Dufrene, M. M. Mojarradi, S. K. Islam, M. N. Ericson

Sensors and Electronics

Research output: Contribution to journal › Conference article › peer-review

13 Scopus citations

Abstract

Two novel reference circuits that exploit unique aspects of SOI technology are reported. The first is a voltage reference based on the G ⁴-FET, a new four-gate transistor possible only in SOI; which achieves a temperature-compensated output voltage without the use of the standard bandgap architecture. The second is a current reference that uses the zero leakage p-well resistor available in many SOI technologies to achieve a low-level, temperature-stable reference current that exceeds the specifications of bulk CMOS low-level current references reported in the literature. Both reference circuits have been implemented in a standard 3.3-V/0.35-μm partially depleted (PD)-SOI process.

Original language	English
Article number	5.2
Pages (from-to)	112-114
Number of pages	3
Journal	Proceedings - IEEE International SOI Conference
State	Published - 2004
Event	2004 IEEE International SOI Conference, Proceedings - Charleston, SC, United States Duration: Oct 4 2004 → Oct 7 2004

Cite this

@article{7787e7adb0e641f991351f61fa313c22,

title = "Temperature-compensated reference circuits for SOI",

abstract = "Two novel reference circuits that exploit unique aspects of SOI technology are reported. The first is a voltage reference based on the G 4-FET, a new four-gate transistor possible only in SOI; which achieves a temperature-compensated output voltage without the use of the standard bandgap architecture. The second is a current reference that uses the zero leakage p-well resistor available in many SOI technologies to achieve a low-level, temperature-stable reference current that exceeds the specifications of bulk CMOS low-level current references reported in the literature. Both reference circuits have been implemented in a standard 3.3-V/0.35-μm partially depleted (PD)-SOI process.",

author = "Terry, {S. C.} and S. Chen and Blalock, {B. J.} and Jackson, {J. R.} and Dufrene, {B. M.} and Mojarradi, {M. M.} and Islam, {S. K.} and Ericson, {M. N.}",

year = "2004",

language = "English",

pages = "112--114",

journal = "Proceedings - IEEE International SOI Conference",

issn = "1078-621X",

note = "2004 IEEE International SOI Conference, Proceedings ; Conference date: 04-10-2004 Through 07-10-2004",

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TY - JOUR

T1 - Temperature-compensated reference circuits for SOI

AU - Terry, S. C.

AU - Chen, S.

AU - Blalock, B. J.

AU - Jackson, J. R.

AU - Dufrene, B. M.

AU - Mojarradi, M. M.

AU - Islam, S. K.

AU - Ericson, M. N.

PY - 2004

Y1 - 2004

N2 - Two novel reference circuits that exploit unique aspects of SOI technology are reported. The first is a voltage reference based on the G 4-FET, a new four-gate transistor possible only in SOI; which achieves a temperature-compensated output voltage without the use of the standard bandgap architecture. The second is a current reference that uses the zero leakage p-well resistor available in many SOI technologies to achieve a low-level, temperature-stable reference current that exceeds the specifications of bulk CMOS low-level current references reported in the literature. Both reference circuits have been implemented in a standard 3.3-V/0.35-μm partially depleted (PD)-SOI process.

AB - Two novel reference circuits that exploit unique aspects of SOI technology are reported. The first is a voltage reference based on the G 4-FET, a new four-gate transistor possible only in SOI; which achieves a temperature-compensated output voltage without the use of the standard bandgap architecture. The second is a current reference that uses the zero leakage p-well resistor available in many SOI technologies to achieve a low-level, temperature-stable reference current that exceeds the specifications of bulk CMOS low-level current references reported in the literature. Both reference circuits have been implemented in a standard 3.3-V/0.35-μm partially depleted (PD)-SOI process.

UR - http://www.scopus.com/inward/record.url?scp=16244384965&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:16244384965

SN - 1078-621X

SP - 112

EP - 114

JO - Proceedings - IEEE International SOI Conference

JF - Proceedings - IEEE International SOI Conference

M1 - 5.2

T2 - 2004 IEEE International SOI Conference, Proceedings

Y2 - 4 October 2004 through 7 October 2004

ER -

Temperature-compensated reference circuits for SOI

Abstract

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