Teaching pipelining and concurrency using hardware description languages

Tsai Chi Huang; Sudhakar Yalamanchili; Roy W. Melton; Philip R. Bingham; Cecil O. Alford

doi:10.1109/MSE.1999.787035

Teaching pipelining and concurrency using hardware description languages

Tsai Chi Huang, Sudhakar Yalamanchili, Roy W. Melton, Philip R. Bingham, Cecil O. Alford

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Relating to a previous simplified VHDL processor model [1], a more advanced synthesized VHDL pipeline microprocessor model was developed and has been used in the second term computer architecture course offered in the School of Electrical and Computer Engineering at the Georgia Institute of Techonology. This paper will first describe the pipeline processor model and its VHDL implementation. Then, it presents various implementation extensions that have been assigned and completed within a satisfactory period by participating students.

Original language	English
Title of host publication	Proceedings - 1999 IEEE International Conference on Microelectronic Systems Education
Subtitle of host publication	Systems Education in the 21st Century, MSE 1999
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	55-56
Number of pages	2
ISBN (Electronic)	0769503128, 9780769503127
DOIs	https://doi.org/10.1109/MSE.1999.787035
State	Published - 1999
Externally published	Yes
Event	1999 IEEE International Conference on Microelectronic Systems Education, MSE 1999 - Arlington, United States Duration: Jul 19 1999 → Jul 21 1999

Publication series

Name	Proceedings - 1999 IEEE International Conference on Microelectronic Systems Education: Systems Education in the 21st Century, MSE 1999

Conference

Conference	1999 IEEE International Conference on Microelectronic Systems Education, MSE 1999
Country/Territory	United States
City	Arlington
Period	07/19/99 → 07/21/99

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10.1109/MSE.1999.787035

Cite this

Huang, T. C., Yalamanchili, S., Melton, R. W., Bingham, P. R., & Alford, C. O. (1999). Teaching pipelining and concurrency using hardware description languages. In Proceedings - 1999 IEEE International Conference on Microelectronic Systems Education: Systems Education in the 21st Century, MSE 1999 (pp. 55-56). Article 787035 (Proceedings - 1999 IEEE International Conference on Microelectronic Systems Education: Systems Education in the 21st Century, MSE 1999). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MSE.1999.787035

Huang, Tsai Chi ; Yalamanchili, Sudhakar ; Melton, Roy W. et al. / Teaching pipelining and concurrency using hardware description languages. Proceedings - 1999 IEEE International Conference on Microelectronic Systems Education: Systems Education in the 21st Century, MSE 1999. Institute of Electrical and Electronics Engineers Inc., 1999. pp. 55-56 (Proceedings - 1999 IEEE International Conference on Microelectronic Systems Education: Systems Education in the 21st Century, MSE 1999).

@inproceedings{1a3e214ff25c424db097d76ec6170f68,

title = "Teaching pipelining and concurrency using hardware description languages",

abstract = "Relating to a previous simplified VHDL processor model [1], a more advanced synthesized VHDL pipeline microprocessor model was developed and has been used in the second term computer architecture course offered in the School of Electrical and Computer Engineering at the Georgia Institute of Techonology. This paper will first describe the pipeline processor model and its VHDL implementation. Then, it presents various implementation extensions that have been assigned and completed within a satisfactory period by participating students.",

author = "Huang, {Tsai Chi} and Sudhakar Yalamanchili and Melton, {Roy W.} and Bingham, {Philip R.} and Alford, {Cecil O.}",

year = "1999",

doi = "10.1109/MSE.1999.787035",

language = "English",

series = "Proceedings - 1999 IEEE International Conference on Microelectronic Systems Education: Systems Education in the 21st Century, MSE 1999",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "55--56",

booktitle = "Proceedings - 1999 IEEE International Conference on Microelectronic Systems Education",

note = "1999 IEEE International Conference on Microelectronic Systems Education, MSE 1999 ; Conference date: 19-07-1999 Through 21-07-1999",

}

Huang, TC, Yalamanchili, S, Melton, RW, Bingham, PR & Alford, CO 1999, Teaching pipelining and concurrency using hardware description languages. in Proceedings - 1999 IEEE International Conference on Microelectronic Systems Education: Systems Education in the 21st Century, MSE 1999., 787035, Proceedings - 1999 IEEE International Conference on Microelectronic Systems Education: Systems Education in the 21st Century, MSE 1999, Institute of Electrical and Electronics Engineers Inc., pp. 55-56, 1999 IEEE International Conference on Microelectronic Systems Education, MSE 1999, Arlington, United States, 07/19/99. https://doi.org/10.1109/MSE.1999.787035

Teaching pipelining and concurrency using hardware description languages. / Huang, Tsai Chi; Yalamanchili, Sudhakar; Melton, Roy W. et al.
Proceedings - 1999 IEEE International Conference on Microelectronic Systems Education: Systems Education in the 21st Century, MSE 1999. Institute of Electrical and Electronics Engineers Inc., 1999. p. 55-56 787035 (Proceedings - 1999 IEEE International Conference on Microelectronic Systems Education: Systems Education in the 21st Century, MSE 1999).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Teaching pipelining and concurrency using hardware description languages

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AU - Yalamanchili, Sudhakar

AU - Melton, Roy W.

AU - Bingham, Philip R.

AU - Alford, Cecil O.

PY - 1999

Y1 - 1999

N2 - Relating to a previous simplified VHDL processor model [1], a more advanced synthesized VHDL pipeline microprocessor model was developed and has been used in the second term computer architecture course offered in the School of Electrical and Computer Engineering at the Georgia Institute of Techonology. This paper will first describe the pipeline processor model and its VHDL implementation. Then, it presents various implementation extensions that have been assigned and completed within a satisfactory period by participating students.

AB - Relating to a previous simplified VHDL processor model [1], a more advanced synthesized VHDL pipeline microprocessor model was developed and has been used in the second term computer architecture course offered in the School of Electrical and Computer Engineering at the Georgia Institute of Techonology. This paper will first describe the pipeline processor model and its VHDL implementation. Then, it presents various implementation extensions that have been assigned and completed within a satisfactory period by participating students.

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DO - 10.1109/MSE.1999.787035

M3 - Conference contribution

AN - SCOPUS:85039982120

T3 - Proceedings - 1999 IEEE International Conference on Microelectronic Systems Education: Systems Education in the 21st Century, MSE 1999

SP - 55

EP - 56

BT - Proceedings - 1999 IEEE International Conference on Microelectronic Systems Education

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 1999 IEEE International Conference on Microelectronic Systems Education, MSE 1999

Y2 - 19 July 1999 through 21 July 1999

ER -

Huang TC, Yalamanchili S, Melton RW, Bingham PR, Alford CO. Teaching pipelining and concurrency using hardware description languages. In Proceedings - 1999 IEEE International Conference on Microelectronic Systems Education: Systems Education in the 21st Century, MSE 1999. Institute of Electrical and Electronics Engineers Inc. 1999. p. 55-56. 787035. (Proceedings - 1999 IEEE International Conference on Microelectronic Systems Education: Systems Education in the 21st Century, MSE 1999). doi: 10.1109/MSE.1999.787035

Teaching pipelining and concurrency using hardware description languages

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