Summary of VERA Core Simulator Performance Improvements

This report describes the performance improvements made to the VERA Core Simulator (VERA CS) during FY2016. At the beginning of the year, a timing study was performed to identify areas of the code where the run-times could be improved. This study identified six broad areas for improvement: • Cross section lookup and CMFD stabilization, • CTF parallel partitioning, • MOC methodology, • Subgroup methodology, • MOC parallel partitioning, and • CMFD Krylov solution techniques. The goal of this work was to reduce the VERA-CS run-times so a complete cycle depletion could be run with 1,000 cores overnight (i.e., the “1,000 core depletion” criterion). This goal was set by our industry partners so they could achieve reasonable turnaround on medium-sized computer clusters. The results presented in this report show a code speed-up by a factor of 5, which successfully satisfies the goal set by industry.