Abstract
A status report is given of the QCDOC project, a massively parallel computer optimized for lattice QCD using system-on-a-chip technology. We describe several of the hardware and software features unique to the QCDOC architecture and present performance figures obtained from simulating the current VHDL design of the QCDOC chip with single-cycle accuracy.
Original language | English |
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Pages (from-to) | 177-183 |
Number of pages | 7 |
Journal | Nuclear Physics B - Proceedings Supplements |
Volume | 106-107 |
DOIs | |
State | Published - Mar 2002 |
Externally published | Yes |
Funding
This research was supported in part by the U.S. Department of Energy, the Institute of Physical and Chemical Research (RIKEN) of Japan, and the U.K. Particle Physics and Astronomy Research Council.
Funders | Funder number |
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Institute of Physical and Chemical Research | |
U.S. Department of Energy | |
RIKEN | |
Particle Physics and Astronomy Research Council |