Abstract
Minimizing parasitic inductance of power modules is needed to advance their electrical performance. Innovation in the past decade has driven down the inductance of SiC half-bridge power modules to around 1-2 nH by using multilayer, embedded, and hybrid structures. Further reduction becomes difficult, mainly limited by the excessive interconnects required for the planar placement of vertical conducting chips. To address this, a vertically stacked-die approach is proposed in this paper, taking advantage of the vertical conducting nature of the SiC chips. With ceramic decoupling capacitors integrated, 0.48 nH overall loop inductance is achieved and validated by experimental measurement. This paper also discusses potential approaches to further reduce the inductance.
| Original language | English |
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| Title of host publication | 2024 IEEE Energy Conversion Congress and Exposition, ECCE 2024 - Proceedings |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 7192-7196 |
| Number of pages | 5 |
| ISBN (Electronic) | 9798350376067 |
| DOIs | |
| State | Published - 2024 |
| Event | 2024 IEEE Energy Conversion Congress and Exposition, ECCE 2024 - Phoenix, United States Duration: Oct 20 2024 → Oct 24 2024 |
Publication series
| Name | 2024 IEEE Energy Conversion Congress and Exposition, ECCE 2024 - Proceedings |
|---|
Conference
| Conference | 2024 IEEE Energy Conversion Congress and Exposition, ECCE 2024 |
|---|---|
| Country/Territory | United States |
| City | Phoenix |
| Period | 10/20/24 → 10/24/24 |
Funding
This material is based on work supported by the US Department of Energy Office of Energy Efficiency and Renewable Energy, Vehicle Technologies Office, under contract number DE-AC05-00OR22725. The authors would like to thank the US Department of Energy's Susan Rogers for her guidance and support.
Keywords
- Silicon-carbide (SiC)
- integrated capacitor
- power module
- stacked-die