Abstract
A simple technique to extract the location and value of parasitic series resistance in junction devices is discussed and an instrument which performs these measurements is described. Measurements of gate series resistance on several high figure of merit junction field-effect transistors are presented. The limitations in noise behavior due to this resistance are discussed.
| Original language | English |
|---|---|
| Pages (from-to) | 470-473 |
| Number of pages | 4 |
| Journal | Nuclear Instruments and Methods in Physics Research, Section A: Accelerators, Spectrometers, Detectors and Associated Equipment |
| Volume | 386 |
| Issue number | 2-3 |
| DOIs | |
| State | Published - Feb 21 1997 |
| Externally published | Yes |
Funding
* Corresponding author. Tel. + I 510 486 5 115. ’ This work was supported in part by the Director, Office of energy Research. U.S. Department of Energy, contract #DE-AC0376SF-00098. Reference to a company or product name does not imply approval or recommendation of the product by the University of California or the U.S. Department of Energy to the Exclusion of others that may be suitable. The authors wish to acknowledge the partial funding provided for this work by AEI-IEEE (Associazione Elet-trotecnicae d Elettronica Italiana-Italian Electric and Electronic Association) through the grant “Isabella Sassi Bonadonna” for the year 1995 and by the Internship Program of the Engineering Division at Lawrence Ber- keley National Laboratory. The authorsa re also in debt to D. Landis, R. Pehl, J. Millaud and E. Beuville for their thoughtful comments and suggestionsd uring the preparation of this paper.
| Funders | Funder number |
|---|---|
| Associazione Elet-trotecnicae d Elettronica Italiana-Italian Electric and Electronic Association | |
| Office of Energy Research and Development |