Simulations of busy probabilities in the ALPIDE chip and the upgraded ALICE ITS detector

ALICE ITS collaboration

Simulations of busy probabilities in the ALPIDE chip and the upgraded ALICE ITS detector

ALICE ITS collaboration

Research output: Contribution to journal › Conference article › peer-review

Abstract

For the Long Shutdown 2 (LS2) upgrade of the ITS detector in the ALICE experiment at the LHC, a novel pixel detector chip, the ALPIDE chip, has been developed. In the event of busy ALPIDE chips in the ITS detector, the readout electronics may need to take appropriate action to minimize loss of data. This paper presents a lightweight, statistical simulation model for the ALPIDE chip and the upgraded ITS detector, developed using the SystemC framework. The purpose of the model is to quantify the probability of a busy condition and the data taking efficiency of the ALPIDE chips under various conditions, and to apply this knowledge during the development of the readout electronics and firmware.

Original language	English
Journal	Proceedings of Science
Volume	2017-September
State	Published - 2017
Externally published	Yes
Event	2017 Topical Workshop on Electronics for Particle Physics, TWEPP 2017 - Santa Cruz, United States Duration: Sep 11 2017 → Sep 14 2017

Cite this

@article{b1a249bcb46146779bf12b3ff2ef3700,

title = "Simulations of busy probabilities in the ALPIDE chip and the upgraded ALICE ITS detector",

abstract = "For the Long Shutdown 2 (LS2) upgrade of the ITS detector in the ALICE experiment at the LHC, a novel pixel detector chip, the ALPIDE chip, has been developed. In the event of busy ALPIDE chips in the ITS detector, the readout electronics may need to take appropriate action to minimize loss of data. This paper presents a lightweight, statistical simulation model for the ALPIDE chip and the upgraded ITS detector, developed using the SystemC framework. The purpose of the model is to quantify the probability of a busy condition and the data taking efficiency of the ALPIDE chips under various conditions, and to apply this knowledge during the development of the readout electronics and firmware.",

author = "\{ALICE ITS collaboration\} and Nesbo, \{S. V.\} and J. Alme and M. Bonora and P. Giubilato and H. Helstrup and S. Hristozkov and Rinella, \{G. Aglieri\} and D. R{\"o}hrich and J. Schambach and R. Shahoyan and K. Ullaland",

note = "Publisher Copyright: {\textcopyright} Copyright owned by the author(s) under the terms of the Creative Commons.; 2017 Topical Workshop on Electronics for Particle Physics, TWEPP 2017 ; Conference date: 11-09-2017 Through 14-09-2017",

year = "2017",

language = "English",

volume = "2017-September",

journal = "Proceedings of Science",

issn = "1824-8039",

publisher = "Sissa Medialab",

}

TY - JOUR

T1 - Simulations of busy probabilities in the ALPIDE chip and the upgraded ALICE ITS detector

AU - ALICE ITS collaboration

AU - Nesbo, S. V.

AU - Alme, J.

AU - Bonora, M.

AU - Giubilato, P.

AU - Helstrup, H.

AU - Hristozkov, S.

AU - Rinella, G. Aglieri

AU - Röhrich, D.

AU - Schambach, J.

AU - Shahoyan, R.

AU - Ullaland, K.

PY - 2017

Y1 - 2017

N2 - For the Long Shutdown 2 (LS2) upgrade of the ITS detector in the ALICE experiment at the LHC, a novel pixel detector chip, the ALPIDE chip, has been developed. In the event of busy ALPIDE chips in the ITS detector, the readout electronics may need to take appropriate action to minimize loss of data. This paper presents a lightweight, statistical simulation model for the ALPIDE chip and the upgraded ITS detector, developed using the SystemC framework. The purpose of the model is to quantify the probability of a busy condition and the data taking efficiency of the ALPIDE chips under various conditions, and to apply this knowledge during the development of the readout electronics and firmware.

AB - For the Long Shutdown 2 (LS2) upgrade of the ITS detector in the ALICE experiment at the LHC, a novel pixel detector chip, the ALPIDE chip, has been developed. In the event of busy ALPIDE chips in the ITS detector, the readout electronics may need to take appropriate action to minimize loss of data. This paper presents a lightweight, statistical simulation model for the ALPIDE chip and the upgraded ITS detector, developed using the SystemC framework. The purpose of the model is to quantify the probability of a busy condition and the data taking efficiency of the ALPIDE chips under various conditions, and to apply this knowledge during the development of the readout electronics and firmware.

UR - https://www.scopus.com/pages/publications/85050468448

M3 - Conference article

AN - SCOPUS:85050468448

SN - 1824-8039

VL - 2017-September

JO - Proceedings of Science

JF - Proceedings of Science

T2 - 2017 Topical Workshop on Electronics for Particle Physics, TWEPP 2017

Y2 - 11 September 2017 through 14 September 2017

ER -

Simulations of busy probabilities in the ALPIDE chip and the upgraded ALICE ITS detector

Abstract

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