Simulation of large-scale HPC architectures

Ian S. Jones, Christian Engelmann

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

13 Scopus citations

Abstract

The Extreme-scale Simulator (xSim) is a recently developed performance investigation toolkit that permits running high-performance computing (HPC) applications in a controlled environment with millions of concurrent execution threads. It allows observing parallel application performance properties in a simulated extreme-scale HPC system to further assist in HPC hardware and application software co-design on the road toward multi-petascale and exascale computing. This paper presents a newly implemented network model for the xSim performance investigation toolkit that is capable of providing simulation support for a variety of HPC network architectures with the appropriate trade-off between simulation scalability and accuracy. The taken approach focuses on a scalable distributed solution with latency and bandwidth restrictions for the simulated network. Different network architectures, such as star, ring, mesh, torus, twisted torus and tree, as well as hierarchical combinations, such as to simulate network-on-chip and network-on-node, are supported. Network traffic congestion modeling is omitted to gain simulation scalability by reducing simulation accuracy.

Original languageEnglish
Title of host publicationProceedings - 2011 International Conference on Parallel Processing Workshops, ICPPW 2011
Pages447-456
Number of pages10
DOIs
StatePublished - 2011
Event2011 International Conference on Parallel Processing Workshops, ICPPW 2011 - Taipei City, Taiwan, Province of China
Duration: Sep 13 2011Sep 16 2011

Publication series

NameProceedings of the International Conference on Parallel Processing Workshops
ISSN (Print)1530-2016

Conference

Conference2011 International Conference on Parallel Processing Workshops, ICPPW 2011
Country/TerritoryTaiwan, Province of China
CityTaipei City
Period09/13/1109/16/11

Keywords

  • Hardware/software co-design
  • High-performance computing
  • Message Passing Interface
  • Parallel discrete event simulation
  • Performance evaluation

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