SiC MOSFET design considerations for reliable high voltage operation

P. A. Losee, A. Bolotnikov, L. C. Yu, G. Dunne, D. Esler, J. Erlbaum, B. Rowden, A. Gowda, A. Halverson, R. Ghandi, P. Sandvik, L. Stevanovic, R. Hristov

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

34 Scopus citations

Abstract

SiC MOSFETs have demonstrated continued performance improvement and maturation in the areas of Gate oxide stability and reliability over the past years. While necessary, this alone is not sufficient to achieve reliable high voltage operation. In this paper, the design constraints impacting high voltage reliability and their impact on SiC MOSFET performance at useful operating conditions are discussed. Experimental results are demonstrated with industry benchmark, reliable operation of up to Tj=200°C with 1.2kV/25mOhm SiC MOSFETs and Tj=175°C, 1.7kV/450A all-SiC MOSFET Dual-Switch modules. Avalanche ruggedness of the high-performance devices is also demonstrated with single-pulse energy densities of 9-15J/cm2 recorded with Drain currents as high as ID= 90A for 0.2cm2 die.

Original languageEnglish
Title of host publication2017 International Reliability Physics Symposium, IRPS 2017
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2A2.1-2A2.8
ISBN (Electronic)9781509066407
DOIs
StatePublished - May 30 2017
Externally publishedYes
Event2017 International Reliability Physics Symposium, IRPS 2017 - Monterey, United States
Duration: Apr 2 2017Apr 6 2017

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Conference

Conference2017 International Reliability Physics Symposium, IRPS 2017
Country/TerritoryUnited States
CityMonterey
Period04/2/1704/6/17

Keywords

  • Avalanche
  • Cell Design
  • Drain Bias
  • HTRB
  • SiC MOSFET
  • UIS

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