Scalable NUMA-aware persistent B+-tree for non-volatile memory devices

Safdar Jamil, Abdul Salam, Awais Khan, Bernd Burgstaller, Sung Soon Park, Youngjae Kim

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

Emerging manycore servers with Intel DC persistent memory (DCPM) are equipped with hundreds of CPU cores on multiple CPU sockets. Such servers are designed to guarantee high performance and scalability. Several recent studies proposed persistent fault-tolerant indexes for DCPM. Fast & Fair (F&F) is the state-of-the-art concurrent variant of the B+-tree for DCPM. However, its adoption on manycore servers is hampered by scalability limitations due to lengthy, lock-based synchronization including structure modification operations. The lack of NUMA awareness induces further performance overhead from remote memory accesses. In this paper, we propose F3-tree, a concurrent, NUMA-aware and persistent future-based B+-tree for DCPM servers. F3-tree relies on per-thread local future objects and a global B+-tree. To introduce NUMA awareness and minimize remote memory accesses, F3-tree adopts per-socket dedicated asynchronous evaluation threads to checkpoint future objects to the global B+-tree. F3-tree employs an in-memory hash table to mitigate the read overhead of key searches over the future objects. We implemented F3-tree atop F&F and evaluated its performance on Linux using both synthetic and realistic workloads. Our evaluation shows that F3-tree outperforms F&F on average by 3.4× and 5× without and with NUMA awareness, respectively.

Original languageEnglish
Pages (from-to)2865-2881
Number of pages17
JournalCluster Computing
Volume26
Issue number5
DOIs
StatePublished - Oct 2023
Externally publishedYes

Funding

This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MSIT) (No. NRF-2021R1A2C2014386) and by the Institute of Information and Communications Technology Planning and Evaluation (IITP), Korea government (MSIT) (Development of low-latency storage module for I/O intensive edge data processing) under grant No. 2020-0-00104. This manuscript has been authored by UT-Battelle, LLC under Contract No. DE-AC05-00OR22725 with the U.S. Department of Energy. The United States Government retains and the publisher, by accepting the article for publication, acknowledges that the United States Government retains a non-exclusive, paid up, irrevocable, world-wide license to publish or reproduce the published form of the manuscript, or allow others to do so, for United States Government purposes. The Department of Energy will provide public access to these results of federally sponsored research in accordance with the DOE Public Access Plan ( http://energy.gov/downloads/doe-public-access-plan ). This research used resources of the Oak Ridge Leadership Computing Facility at the Oak Ridge National Laboratory, which is supported by the Office of Science of the U.S. Department of Energy under Contract No. DE-AC05-00OR22725.

FundersFunder number
Institute of Information and Communications Technology Planning and Evaluation
U.S. Department of Energy
Office of Science
Ministry of Science, ICT and Future PlanningNRF-2021R1A2C2014386
National Research Foundation of Korea
Institute for Information and Communications Technology PromotionDE-AC05-00OR22725, 2020-0-00104

    Keywords

    • B-tree
    • Indexing data structures
    • NUMA-aware architecture
    • Performance scalability
    • Persistent memory

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