Resource Efficient Implementation of Low Power LDPC Based CDMA Architecture

In this study, LDPC codes based low power multi-user CDMA architecture is proposed. Also, a modified Min-Sum algorithm for LDPC Decoder design is built and used in the proposed architecture. Min-sum iterative decoder has a reduced complexity in terms of architecture-algorithm transformation, compared to other LDPC Decoding algorithms. The architecture is designed for LDPC encoder and the variants of Min-sum decoder. The architecture is synthesized on Xilinx and Synopsys tool targeted to 90 run device. It is found from the synthesis report of the proposed architecture that it reduces the area and power overhead when compared with the conventional architecture design.