@inproceedings{01d8ab2932864834a708d713b1086d01,
title = "Reducing soft-error vulnerability of caches using data compression",
abstract = "With ongoing chip miniaturization and voltage scaling, particle strike-induced soft errors present increasingly severe threat to the reliability of on-chip caches. In this paper, we present a technique to reduce the vulnerability of caches to soft-errors. Our technique uses data compression to reduce the number of vulnerable data bits in the cache and performs selective duplication of more critical data-bits to provide extra protection to them. Microarchitectural simulations have shown that our technique is effective in reducing cache vulnerability and outperforms another technique. For single and dual-core system configuration, the average reduction in cache vulnerability is 5.59× and 8.44×, respectively. Also, the implementation and performance overheads of our technique are minimal and it is useful for a broad range of workloads.",
keywords = "Cache, Data compression, Fault-tolerance, Reliability, Resilience, Soft/transient error, Vulnerability",
author = "Sparsh Mittal and Vetter, {Jeffrey S.}",
note = "Publisher Copyright: {\textcopyright} 2016 ACM.; 26th ACM Great Lakes Symposium on VLSI, GLSVLSI 2016 ; Conference date: 18-05-2016 Through 20-05-2016",
year = "2016",
month = may,
day = "18",
doi = "10.1145/2902961.2902977",
language = "English",
series = "Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI",
publisher = "Association for Computing Machinery",
pages = "197--202",
booktitle = "GLSVLSI 2016 - Proceedings of the 2016 ACM Great Lakes Symposium on VLSI",
}