TY - GEN
T1 - QuaSi
T2 - 5th IEEE International Conference on Quantum Computing and Engineering, QCE 2024
AU - Lu, Chao
AU - Choudhury, Navnil
AU - Basu, Kanad
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - Quantum circuit transpilation facilitates the decomposition of complex operations into simpler hardware-compatible gates. This results in significant changes to the input circuit, and consequently, it becomes imperative to verify the correctness of the transpilation process. Quantum circuit equivalence checking is used to verify the operational equivalence of large quantum circuits to ensure the correctness of computation. Although small quantum circuits can be simulated easily on a classical computer without transpilation, this approach is unscalable for larger, more complex quantum circuits. Furthermore, a scalable quantum equivalence checking algorithm exhibiting subpar performance when applied to larger quantum circuits lacks reliability. Therefore, an equivalence-checking algorithm with scalability and acceptable performance is necessary to verify large quantum circuits. In this paper, we propose QuaSi, a simulation-based verification methodology designed to generate distinct test cases to achieve a scalable and reliable quantum circuit equivalence-checking. Our proposed approach surpasses existing state-of-the-art simulation-based methodologies by boosting the success rate of verification, in addition to reducing the verification latency. When evaluating using large benchmarks with up to 130 qubits, QuaSi furnished significantly improved performance compared to existing approaches in all types of scenarios. Furthermore, we proposed an algorithm to locate the erroneous gates to facilitate debugging the transpilation process.
AB - Quantum circuit transpilation facilitates the decomposition of complex operations into simpler hardware-compatible gates. This results in significant changes to the input circuit, and consequently, it becomes imperative to verify the correctness of the transpilation process. Quantum circuit equivalence checking is used to verify the operational equivalence of large quantum circuits to ensure the correctness of computation. Although small quantum circuits can be simulated easily on a classical computer without transpilation, this approach is unscalable for larger, more complex quantum circuits. Furthermore, a scalable quantum equivalence checking algorithm exhibiting subpar performance when applied to larger quantum circuits lacks reliability. Therefore, an equivalence-checking algorithm with scalability and acceptable performance is necessary to verify large quantum circuits. In this paper, we propose QuaSi, a simulation-based verification methodology designed to generate distinct test cases to achieve a scalable and reliable quantum circuit equivalence-checking. Our proposed approach surpasses existing state-of-the-art simulation-based methodologies by boosting the success rate of verification, in addition to reducing the verification latency. When evaluating using large benchmarks with up to 130 qubits, QuaSi furnished significantly improved performance compared to existing approaches in all types of scenarios. Furthermore, we proposed an algorithm to locate the erroneous gates to facilitate debugging the transpilation process.
KW - Quantum computing
KW - quantum verification
KW - simulation testing
UR - https://www.scopus.com/pages/publications/85217359827
U2 - 10.1109/QCE60285.2024.00123
DO - 10.1109/QCE60285.2024.00123
M3 - Conference contribution
AN - SCOPUS:85217359827
T3 - Proceedings - IEEE Quantum Week 2024, QCE 2024
SP - 1037
EP - 1047
BT - Technical Papers Program
A2 - Culhane, Candace
A2 - Byrd, Greg T.
A2 - Muller, Hausi
A2 - Alexeev, Yuri
A2 - Alexeev, Yuri
A2 - Sheldon, Sarah
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 15 September 2024 through 20 September 2024
ER -