TY - JOUR
T1 - QCDOC
T2 - A 10-teraflops scale computer for lattice QCD
AU - Chen, D.
AU - Christ, N. H.
AU - Cristian, C.
AU - Dong, Z.
AU - Gara, A.
AU - Garg, K.
AU - Joo, B.
AU - Kim, C.
AU - Levkova, L.
AU - Liao, X.
AU - Mawhinney, R. D.
AU - Ohta, S.
AU - Wettig, T.
PY - 2001/3
Y1 - 2001/3
N2 - The architecture of a new class of computers, optimized for lattice QCD calculations, is described. An individual node is based on a single integrated circuit containing a PowerPC 32-bit integer processor with a 1 Gflops 64-bit IEEE floating point unit, 4 Mbyte of memory, 8 Gbit/sec nearest-neighbor communications and additional control and diagnostic circuitry. The machine's name, QCDOC, derives from "QCD On a Chip".
AB - The architecture of a new class of computers, optimized for lattice QCD calculations, is described. An individual node is based on a single integrated circuit containing a PowerPC 32-bit integer processor with a 1 Gflops 64-bit IEEE floating point unit, 4 Mbyte of memory, 8 Gbit/sec nearest-neighbor communications and additional control and diagnostic circuitry. The machine's name, QCDOC, derives from "QCD On a Chip".
UR - http://www.scopus.com/inward/record.url?scp=0035285517&partnerID=8YFLogxK
U2 - 10.1016/S0920-5632(01)01014-3
DO - 10.1016/S0920-5632(01)01014-3
M3 - Article
AN - SCOPUS:0035285517
SN - 0920-5632
VL - 94
SP - 825
EP - 832
JO - Nuclear Physics B - Proceedings Supplements
JF - Nuclear Physics B - Proceedings Supplements
IS - 1-3
ER -