PVT compensation for wilkinson single-slope measurement systems

K. V. Tham; C. Ulaganathan; N. Nambiar; R. L. Greenwell; C. L. Britton; M. N. Ericson; J. Holleman; B. J. Blalock

doi:10.1109/TNS.2012.2212722

PVT compensation for wilkinson single-slope measurement systems

K. V. Tham, C. Ulaganathan, N. Nambiar, R. L. Greenwell, C. L. Britton, M. N. Ericson, J. Holleman, B. J. Blalock

Sensors and Electronics

Research output: Contribution to journal › Article › peer-review

8 Scopus citations

Abstract

A pulse-width locked loop (PWLL) circuit is reported that compensates for process, voltage, and temperature (PVT) variations of a linear ramp generator within a 12-bit multi-channel Wilkinson (single-slope integrating) Analog-to-Digital converter (ADC). This PWLL was designed and fabricated in a 0.5-μm Silicon Germanium (SiGe) BiCMOS process. Simulation and silicon measurement data are shown that demonstrate a large improvement in the accuracy of the PVT-compensated ADC over the uncompensated ADC.

Original language	English
Article number	6307900
Pages (from-to)	2444-2450
Number of pages	7
Journal	IEEE Transactions on Nuclear Science
Volume	59
Issue number	5 PART 3
DOIs	https://doi.org/10.1109/TNS.2012.2212722
State	Published - 2012

Funding

ACKNOWLEDGMENT This work was supported by the NASA ETDP program, under grant NNL06AA29C—Silicon Germanium Integrated Electronics for Extreme Environments. We are grateful to M. Watson, A. Keys, and the SiGe ETDP team led by Prof. J. Cressler of Georgia Tech for their contributions.

Funders	Funder number
National Aeronautics and Space Administration	NNL06AA29C

Keywords

Analog-to-digital converter (ADC)
PWLL
linear system
process, voltage, and temperature (PVT) compensation
pulse-width modulator (PWM)
single-slope measurement systems

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10.1109/TNS.2012.2212722

Cite this

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title = "PVT compensation for wilkinson single-slope measurement systems",

abstract = "A pulse-width locked loop (PWLL) circuit is reported that compensates for process, voltage, and temperature (PVT) variations of a linear ramp generator within a 12-bit multi-channel Wilkinson (single-slope integrating) Analog-to-Digital converter (ADC). This PWLL was designed and fabricated in a 0.5-μm Silicon Germanium (SiGe) BiCMOS process. Simulation and silicon measurement data are shown that demonstrate a large improvement in the accuracy of the PVT-compensated ADC over the uncompensated ADC.",

keywords = "Analog-to-digital converter (ADC), PWLL, linear system, process, voltage, and temperature (PVT) compensation, pulse-width modulator (PWM), single-slope measurement systems",

author = "Tham, {K. V.} and C. Ulaganathan and N. Nambiar and Greenwell, {R. L.} and Britton, {C. L.} and Ericson, {M. N.} and J. Holleman and Blalock, {B. J.}",

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AU - Tham, K. V.

AU - Ulaganathan, C.

AU - Nambiar, N.

AU - Greenwell, R. L.

AU - Britton, C. L.

AU - Ericson, M. N.

AU - Holleman, J.

AU - Blalock, B. J.

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AB - A pulse-width locked loop (PWLL) circuit is reported that compensates for process, voltage, and temperature (PVT) variations of a linear ramp generator within a 12-bit multi-channel Wilkinson (single-slope integrating) Analog-to-Digital converter (ADC). This PWLL was designed and fabricated in a 0.5-μm Silicon Germanium (SiGe) BiCMOS process. Simulation and silicon measurement data are shown that demonstrate a large improvement in the accuracy of the PVT-compensated ADC over the uncompensated ADC.

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KW - PWLL

KW - linear system

KW - process, voltage, and temperature (PVT) compensation

KW - pulse-width modulator (PWM)

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PVT compensation for wilkinson single-slope measurement systems

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Keywords

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