TY - GEN
T1 - Power balancing in an emulated exascale environment
AU - Maiterth, Matthias
AU - Schulz, Martin
AU - Kranzlmüller, Dieter
AU - Rountree, Barry
N1 - Publisher Copyright:
© 2016 IEEE.
PY - 2016/7/18
Y1 - 2016/7/18
N2 - Optimal utilization of power is a major concern for HPC, and is one of the focus points on the path towards exascale and approaches range from chip level to facility wide solutions. In order to evaluate the implications of these approaches and their impact on future system design, we need to understand their interaction with applications as well as their performance impact. In this work we describe the GREMLIN framework, a general framework to emulate system changes on existing platforms by resource restriction or event injection. We use this framework to understand the behavior of applications executed on power limited systems and to evaluate a solution for one of the problems resulting from operating under a power limit: the translation of manufacturing variability into heterogeneous performance, as observed in power limited HPC environments. We show that in a power limited environment manufacturing variability is a key source of performance imbalances and thus non-optimal execution. We propose a Power Balancer for redistribution of unused power and show performance gains of up to 1.5% at small to medium node counts.
AB - Optimal utilization of power is a major concern for HPC, and is one of the focus points on the path towards exascale and approaches range from chip level to facility wide solutions. In order to evaluate the implications of these approaches and their impact on future system design, we need to understand their interaction with applications as well as their performance impact. In this work we describe the GREMLIN framework, a general framework to emulate system changes on existing platforms by resource restriction or event injection. We use this framework to understand the behavior of applications executed on power limited systems and to evaluate a solution for one of the problems resulting from operating under a power limit: the translation of manufacturing variability into heterogeneous performance, as observed in power limited HPC environments. We show that in a power limited environment manufacturing variability is a key source of performance imbalances and thus non-optimal execution. We propose a Power Balancer for redistribution of unused power and show performance gains of up to 1.5% at small to medium node counts.
KW - Exascale Emulation
KW - Power Balancing
KW - Power-Constrained HPC
KW - RAPL
KW - System Software
KW - Tools
UR - http://www.scopus.com/inward/record.url?scp=84991581713&partnerID=8YFLogxK
U2 - 10.1109/IPDPSW.2016.142
DO - 10.1109/IPDPSW.2016.142
M3 - Conference contribution
AN - SCOPUS:84991581713
T3 - Proceedings - 2016 IEEE 30th International Parallel and Distributed Processing Symposium, IPDPS 2016
SP - 1142
EP - 1149
BT - Proceedings - 2016 IEEE 30th International Parallel and Distributed Processing Symposium, IPDPS 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 30th IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2016
Y2 - 23 May 2016 through 27 May 2016
ER -