Picosecond load-adaptive output-buffer-delay modeling circuit for a hierarchical delay-locked loop

A novel technique for the load-adaptive modeling circuit of an output buffer by using an asynchronous time-measurement circuit (ATMC) in a hierarchical delay-locked loop (DLL) is presented. This approach can be adjusted to the small skew difference between the output-buffer delay and the replica-modeling delay by adopting a new fine vernier-scaled time-measurement circuit. The achieved data shows a resolution of several tens of picoseconds by using a HSPICE simulation with a 0.35-μm complementary metal-oxide-semiconductor (CMOS) process.