Performance Potential of Mixed Data Management Modes for Heterogeneous Memory Systems

T. Chad Effler, Michael R. Jantz, Terry Jones

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Many high-performance systems now include different types of memory devices within the same compute platform to meet strict performance and cost constraints. Such heterogeneous memory systems often include an upper-level tier with better performance, but limited capacity, and lower-level tiers with higher capacity, but less bandwidth and longer latencies for reads and writes. To utilize the different memory layers efficiently, current systems rely on hardware-directed, memory -side caching or they provide facilities in the operating system (OS) that allow applications to make their own data-tier assignments. Since these data management options each come with their own set of trade-offs, many systems also include mixed data management configurations that allow applications to employ hardware- and software-directed management simultaneously, but for different portions of their address space. Despite the opportunity to address limitations of stand-alone data management options, such mixed management modes are under-utilized in practice, and have not been evaluated in prior studies of complex memory hardware. In this work, we develop custom program profiling, configurations, and policies to study the potential of mixed data management modes to outperform hardware- or software-based management schemes alone. Our experiments, conducted on an Intel ® Knights Landing platform with high-bandwidth memory, demonstrate that the mixed data management mode achieves the same or better performance than the best stand-alone option for five memory intensive benchmark applications (run separately and in isolation), resulting in an average speedup compared to the best stand-alone policy of over 10 %, on average.

Original languageEnglish
Title of host publicationProceedings of MCHPC 2020
Subtitle of host publicationWorkshop on Memory Centric High Performance Computing, Held in conjunction with SC 2020: The International Conference for High Performance Computing, Networking, Storage and Analysis
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages10-16
Number of pages7
ISBN (Electronic)9781665422789
DOIs
StatePublished - Nov 2020
Event2020 IEEE/ACM Workshop on Memory Centric High Performance Computing, MCHPC 2020 - Virtual, Atlanta, United States
Duration: Nov 11 2020 → …

Publication series

NameProceedings of MCHPC 2020: Workshop on Memory Centric High Performance Computing, Held in conjunction with SC 2020: The International Conference for High Performance Computing, Networking, Storage and Analysis

Conference

Conference2020 IEEE/ACM Workshop on Memory Centric High Performance Computing, MCHPC 2020
Country/TerritoryUnited States
CityVirtual, Atlanta
Period11/11/20 → …

Funding

ACKNOWLEDGEMENTS We thank the anonymous reviewers for their thoughtful comments and feedback. This research was supported by the Exascale Computing Project (17-SC-20-SC), a collaborative effort of the U.S. Department of Energy Office of Science and the National Nuclear Security Administration, with additional contributions from the National Science Foundation under CNS-1943305.

FundersFunder number
National Science FoundationCNS-1943305, 1943305
U.S. Department of Energy
National Nuclear Security Administration

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