TY - GEN
T1 - Performance impact of a slower main memory
T2 - 2nd International Symposium on Memory Systems, MEMSYS 2016
AU - Asifuzzaman, Kazi
AU - Pavlovic, Milan
AU - Radulovic, Milan
AU - Zaragoza, David
AU - Kwon, Ohseong
AU - Ryoo, Kyung Chang
AU - Radojkovic, Petar
N1 - Publisher Copyright:
© 2016 ACM.
PY - 2016/10/3
Y1 - 2016/10/3
N2 - In high-performance computing (HPC), significant effort is invested in research and development of novel memory technologies. One of them is Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) - byte-addressable, high-endurance non-volatile memory with slightly higher access time than DRAM. In this study, we conduct a preliminary assessment of HPC system performance impact with STT-MRAM main memory with recent industry estimations. Reliable timing parameters of STT-MRAM devices are unavailable, so we also perform a sensitivity analysis that correlates overall system slowdown trend with respect to average device latency. Our results demonstrate that the overall system performance of large HPC clusters is not particularly sensitive to main-memory latency. Therefore, STT-MRAM, as well as any other emerging non-volatile memories with comparable density and access time, can be a viable option for future HPC memory system design.
AB - In high-performance computing (HPC), significant effort is invested in research and development of novel memory technologies. One of them is Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) - byte-addressable, high-endurance non-volatile memory with slightly higher access time than DRAM. In this study, we conduct a preliminary assessment of HPC system performance impact with STT-MRAM main memory with recent industry estimations. Reliable timing parameters of STT-MRAM devices are unavailable, so we also perform a sensitivity analysis that correlates overall system slowdown trend with respect to average device latency. Our results demonstrate that the overall system performance of large HPC clusters is not particularly sensitive to main-memory latency. Therefore, STT-MRAM, as well as any other emerging non-volatile memories with comparable density and access time, can be a viable option for future HPC memory system design.
KW - High-performance computing
KW - Main memory
KW - Stt-MRAM
UR - http://www.scopus.com/inward/record.url?scp=84995380604&partnerID=8YFLogxK
U2 - 10.1145/2989081.2989082
DO - 10.1145/2989081.2989082
M3 - Conference contribution
AN - SCOPUS:84995380604
T3 - ACM International Conference Proceeding Series
SP - 40
EP - 49
BT - MEMSYS 2016 - Proceedings of the International Symposium on Memory Systems
PB - Association for Computing Machinery
Y2 - 3 October 2016 through 6 October 2016
ER -
