Performance evaluation of the cray X1 distributed shared-memory architecture

Thomas H. Dunigan; Jeffrey S. Vetter; James B. White; Patrick H. Worley

doi:10.1109/MM.2005.20

Performance evaluation of the cray X1 distributed shared-memory architecture

Thomas H. Dunigan, Jeffrey S. Vetter, James B. White, Patrick H. Worley

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36 Scopus citations

Abstract

The Cray X1 supercomputer's distributed shared memory presents a 64-bit global address space that is directly addressable from every MSP with an interconnect bandwidth per computation rate of 1 byte/flop. Our results show that this high bandwidth and low latency for remote memory accesses translate into improved application performance on important applications.

Original language	English
Pages (from-to)	30-40
Number of pages	11
Journal	IEEE Micro
Volume	25
Issue number	1
DOIs	https://doi.org/10.1109/MM.2005.20
State	Published - Jan 2005

Funding

We gratefully acknowledge Cray Inc. for its ongoing cooperation and, in particular, Steve Scott, James Schwarzmeier, and Nathan Wichmann. The work described in this article was sponsored by the Office of Mathematical, Information, and Computational Sciences, Office of Science, US Department of Energy under Contract No. DE-AC05-00OR22725 with UT-Battelle, LLC. Accordingly, the US government retains a nonexclusive, royalty-free license to publish or reproduce the published form of this contribution, or allow others to do so, for US Government purposes.

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10.1109/MM.2005.20

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Performance evaluation of the cray X1 distributed shared-memory architecture

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