Abstract
We study the performance of high-speed interconnects using a set of communication micro-benchmarks. The goal is to identify certain limiting factors and bottlenecks with these interconnects. Our micro-benchmarks are based on dense communication patterns with different communicating partners and varying degrees of these partners. We tested our micro-benchmarks on five platforms: an IBM system of 68-node 16-way Power3, interconnected by a SP switch2; another IBM system of 264-node 4-way Power PC 604e, interconnected by a SP switch; a Compaq cluster of 128-node 4-way ES40/EV67 processor, interconnected by an Quadrics interconnect; an Intel cluster of 16-node dual-CPU Xeon, interconnected by an Quadrics interconnect; and a cluster of 22-node Sun Ultra Sparc, interconnected by an Ethernet network. Our results show many limitations of these networks including the memory contention within a node as the number of communicating processors increased and the limitations of the network interface for communication between multiple processors of different nodes.
| Original language | English |
|---|---|
| Article number | 1488742 |
| Pages (from-to) | 554-561 |
| Number of pages | 8 |
| Journal | Proceedings of the International Conference on Parallel Processing Workshops |
| Volume | 2005 |
| DOIs | |
| State | Published - 2005 |
| Event | International Conference on Parallel Processing Workshops 2005, ICPP 2005 - Oslo, Norway Duration: Jun 14 2005 → Jun 17 2005 |
Funding
Part of this work was performed under the auspices of the US Dept. of Energy by University of California LLNL under contract W-7405-Eng-48.
| Funders | Funder number |
|---|---|
| U.S. Department of Energy | |
| University of California | W-7405-Eng-48 |