Performance evaluation of high-speed interconnects using dense communication patterns

Rod Fatoohi, Ken Kardys, Sumy Koshy, Soundarya Sivaramakrishnan, Jeffrey S. Vetter

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

We study the performance of high-speed interconnects using a set of communication micro-benchmarks. The goal is to identify certain limiting factors and bottlenecks with these interconnects. Our micro-benchmarks are based on dense communication patterns with different communicating partners and varying degrees of these partners. We tested our micro-benchmarks on five platforms: an IBM system of 68-node 16-way Power3, interconnected by a SP switch2; another IBM system of 264-node 4-way Power PC 604e, interconnected by an SP switch; a Compaq cluster of 128-node 4-way ES40/EV67 processor, interconnected by an Quadrics interconnect; an Intel cluster of 16-node dual-CPU Xeon, interconnected by an Quadrics interconnect; and a cluster of 22-node Sun Ultra Sparc, interconnected by an Ethernet network. Our results show many limitations of these networks including the memory contention within a node as the number of communicating processors increased and the limitations of the network interface for communication between multiple processors of different nodes.

Original languageEnglish
Pages (from-to)794-807
Number of pages14
JournalParallel Computing
Volume32
Issue number11-12
DOIs
StatePublished - Dec 2006

Funding

Part of this work was performed under the auspices of the US Dept. of Energy by University of California LLNL under contract W-7405-Eng-48.

Keywords

  • Interconnect architecture
  • Micro-benchmarks
  • Pair-wise communication
  • Performance evaluation

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