Abstract
It is questionable whether DRAM will continue to scale and will meet the needs of next-generation systems. Therefore, significant effort is invested in research and development of novel memory technologies. One of the candidates for next-generation memory is Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM). STT-MRAM is an emerging non-volatile memory with a lot of potential that could be exploited for various requirements of different computing systems. Being a novel technology, STT-MRAM devices are already approaching DRAM in terms of capacity, frequency, and device size. Although STT-MRAM technology got significant attention of various major memory manufacturers, academic research of STT-MRAM main memory remains marginal. This is mainly due to the unavailability of publicly available detailed timing and current parameters of this novel technology, which are required to perform a reliable main memory simulation on performance and power estimation. This study demonstrates an approach to perform a cycle accurate simulation of STT-MRAM main memory, being the first to release detailed timing and current parameters of this technology from academia - essentially enabling researchers to conduct reliable system-level simulation of STT-MRAM using widely accepted existing simulation infrastructure. The results show a fairly narrow overall performance deviation in response to significant variations in key timing parameters, and the power consumption experiments identify the key power component that is mostly affected with STT-MRAM.
| Original language | English |
|---|---|
| Article number | 6 |
| Journal | ACM Transactions on Embedded Computing Systems |
| Volume | 21 |
| Issue number | 1 |
| DOIs | |
| State | Published - Jan 2022 |
| Externally published | Yes |
Funding
Extension of the conference paper: Kazi Asifuzzaman, Rommel Sánchez Verdejo, and Petar Radojković, Enabling a reliable STT-MRAM main memory simulation. In Proceedings of the International Symposium on Memory Systems (MEMSYS), 2017. This work was supported by the Spanish Government (contract PID2019-107255GB) and Generalitat de Catalunya (contracts 2017-SGR-1328 and 2017-SGR-1414). The authors wish to thank Terry Hulett, Duncan Bennett and Ben Cooke from Everspin Technologies Inc., for their technical support. Authors’ addresses: K. Asifuzzaman, Oak Ridge National Laboratory, USA; email: [email protected]; R. S. Verdejo, Barcelona Supercomputing Center & Universitat Politécnica de Catalunya, Spain; email: [email protected]; P. Radojković, Barcelona Supercomputing Center, Spain; email: [email protected]. Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]. © 2022 Association for Computing Machinery. 1539-9087/2022/01-ART6 $15.00 https://doi.org/10.1145/3476838 This work was supported by the Spanish Government (contract PID2019-107255GB) and Generalitat de Catalunya (contracts 2017-SGR-1328 and 2017-SGR-1414). The authors wish to thank Terry Hulett, Duncan Bennett and Ben Cooke from Everspin Technologies Inc., for their technical support.
| Funders | Funder number |
|---|---|
| Everspin Technologies Inc. | |
| Spanish Government | PID2019-107255GB |
| Generalitat de Catalunya | 2017-SGR-1328, 2017-SGR-1414 |
Keywords
- STT-MRAM
- high-performance computing
- main memory