PCCS: Processor-centric contention-aware slowdown model for heterogeneous system-on-chips

Yuanchao Xu; Mehmet E. Belviranli; Xipeng Shen; Jeffrey Vetter

doi:10.1145/3466752.3480101

PCCS: Processor-centric contention-aware slowdown model for heterogeneous system-on-chips

Yuanchao Xu, Mehmet E. Belviranli, Xipeng Shen, Jeffrey Vetter

Computer Science and Mathematics Div

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

9 Scopus citations

Abstract

Many slowdown models have been proposed to characterize memory interference ofworkloads co-running on heterogeneous Systemon- Chips (SoCs). But they are mostly for post-silicon usage. How to effectively consider memory interference in the SoC design stage remains an open problem. This paper presents a new approach to this problem, consisting of a novel processor-centric slowdown modeling methodology and a new three-region interference-conscious slowdown model. The modeling process needs no measurement of corunning of various combinations of applications, but the produced slowdown models can be used to estimate the co-run slowdowns of arbitrary workloads on various SoC designs that embed a newer generation of accelerators, such as deep learning accelerators (DLA), in addition to CPUs and GPUs. The new method reduces average prediction errors of the state-of-art model from 30.3% to 8.7% on GPU, from 13.4% to 3.7% on CPU, from 20.6% to 5.6% on DLA and demonstrates much improved efficacy in guiding SoC designs.

Original language	English
Title of host publication	MICRO 2021 - 54th Annual IEEE/ACM International Symposium on Microarchitecture, Proceedings
Publisher	IEEE Computer Society
Pages	1282-1295
Number of pages	14
ISBN (Electronic)	9781450385572
DOIs	https://doi.org/10.1145/3466752.3480101
State	Published - Oct 18 2021
Event	54th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2021 - Virtual, Online, Greece Duration: Oct 18 2021 → Oct 22 2021

Publication series

Name	Proceedings of the Annual International Symposium on Microarchitecture, MICRO
ISSN (Print)	1072-4451

Conference

Conference	54th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2021
Country/Territory	Greece
City	Virtual, Online
Period	10/18/21 → 10/22/21

Funding

We thank all the anonymous reviewers whose feedback is helpful for improving the final version of the paper. We also thank Seyong Lee, Narasinga Rao Miniskar and Mohammad Alaul Haque Monil, Steve A Moulton for their feedback and support. This material is based upon work supported by the National Science Foundation (NSF) under Grant No. CCF-2124010 and CNS-1717425, the US Department of Energy (DOE) Office of Science under contract no. DE-AC05-00OR22725, the Defense Advanced Research Projects Agency Microsystems Technology Office Domain-Specific System-on-Chip Program and DOE Office of Science, Office of Advanced Scientific Computing Research. Any opinions, findings, and conclusions or recommendations expressed in this material are those of the authors and do not necessarily reflect the views of NSF or DOE.

Keywords

Accelerator Architectures
Performance Models
System-on-Chips

Access to Document

10.1145/3466752.3480101

Cite this

Xu, Y., Belviranli, M. E., Shen, X., & Vetter, J. (2021). PCCS: Processor-centric contention-aware slowdown model for heterogeneous system-on-chips. In MICRO 2021 - 54th Annual IEEE/ACM International Symposium on Microarchitecture, Proceedings (pp. 1282-1295). (Proceedings of the Annual International Symposium on Microarchitecture, MICRO). IEEE Computer Society. https://doi.org/10.1145/3466752.3480101

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abstract = "Many slowdown models have been proposed to characterize memory interference ofworkloads co-running on heterogeneous Systemon- Chips (SoCs). But they are mostly for post-silicon usage. How to effectively consider memory interference in the SoC design stage remains an open problem. This paper presents a new approach to this problem, consisting of a novel processor-centric slowdown modeling methodology and a new three-region interference-conscious slowdown model. The modeling process needs no measurement of corunning of various combinations of applications, but the produced slowdown models can be used to estimate the co-run slowdowns of arbitrary workloads on various SoC designs that embed a newer generation of accelerators, such as deep learning accelerators (DLA), in addition to CPUs and GPUs. The new method reduces average prediction errors of the state-of-art model from 30.3% to 8.7% on GPU, from 13.4% to 3.7% on CPU, from 20.6% to 5.6% on DLA and demonstrates much improved efficacy in guiding SoC designs.",

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Xu, Y, Belviranli, ME, Shen, X & Vetter, J 2021, PCCS: Processor-centric contention-aware slowdown model for heterogeneous system-on-chips. in MICRO 2021 - 54th Annual IEEE/ACM International Symposium on Microarchitecture, Proceedings. Proceedings of the Annual International Symposium on Microarchitecture, MICRO, IEEE Computer Society, pp. 1282-1295, 54th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2021, Virtual, Online, Greece, 10/18/21. https://doi.org/10.1145/3466752.3480101

PCCS: Processor-centric contention-aware slowdown model for heterogeneous system-on-chips. / Xu, Yuanchao; Belviranli, Mehmet E.; Shen, Xipeng et al.
MICRO 2021 - 54th Annual IEEE/ACM International Symposium on Microarchitecture, Proceedings. IEEE Computer Society, 2021. p. 1282-1295 (Proceedings of the Annual International Symposium on Microarchitecture, MICRO).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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Xu Y, Belviranli ME, Shen X, Vetter J. PCCS: Processor-centric contention-aware slowdown model for heterogeneous system-on-chips. In MICRO 2021 - 54th Annual IEEE/ACM International Symposium on Microarchitecture, Proceedings. IEEE Computer Society. 2021. p. 1282-1295. (Proceedings of the Annual International Symposium on Microarchitecture, MICRO). doi: 10.1145/3466752.3480101

PCCS: Processor-centric contention-aware slowdown model for heterogeneous system-on-chips

Abstract

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Keywords

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