TY - JOUR
T1 - Optimizing matrix multiplication for a short-vector SIMD architecture - CELL processor
AU - Kurzak, Jakub
AU - Alvaro, Wesley
AU - Dongarra, Jack
PY - 2009/3
Y1 - 2009/3
N2 - Matrix multiplication is one of the most common numerical operations, especially in the area of dense linear algebra, where it forms the core of many important algorithms, including solvers of linear systems of equations, least square problems, and singular and eigenvalue computations. The STI CELL processor exceeds the capabilities of any other processor available today in terms of peak single precision, floating point performance, aside from special purpose accelerators like Graphics Processing Units (GPUs). In order to fully exploit the potential of the CELL processor for a wide range of numerical algorithms, fast implementation of the matrix multiplication operation is essential. The crucial component is the matrix multiplication kernel crafted for the short vector Single Instruction Multiple Data architecture of the Synergistic Processing Element of the CELL processor. In this paper, single precision matrix multiplication kernels are presented implementing the C = C - A × BT operation and the C = C - A × B operation for matrices of size 64 × 64 elements. For the latter case, the performance of 25.55 Gflop/s is reported, or 99.80% of the peak, using as little as 5.9 kB of storage for code and auxiliary data structures.
AB - Matrix multiplication is one of the most common numerical operations, especially in the area of dense linear algebra, where it forms the core of many important algorithms, including solvers of linear systems of equations, least square problems, and singular and eigenvalue computations. The STI CELL processor exceeds the capabilities of any other processor available today in terms of peak single precision, floating point performance, aside from special purpose accelerators like Graphics Processing Units (GPUs). In order to fully exploit the potential of the CELL processor for a wide range of numerical algorithms, fast implementation of the matrix multiplication operation is essential. The crucial component is the matrix multiplication kernel crafted for the short vector Single Instruction Multiple Data architecture of the Synergistic Processing Element of the CELL processor. In this paper, single precision matrix multiplication kernels are presented implementing the C = C - A × BT operation and the C = C - A × B operation for matrices of size 64 × 64 elements. For the latter case, the performance of 25.55 Gflop/s is reported, or 99.80% of the peak, using as little as 5.9 kB of storage for code and auxiliary data structures.
KW - Instruction level parallelism
KW - Loop optimizations
KW - Single Instruction Multiple Data
KW - Synergistic Processing Element
KW - Vectorization
UR - http://www.scopus.com/inward/record.url?scp=60649099576&partnerID=8YFLogxK
U2 - 10.1016/j.parco.2008.12.010
DO - 10.1016/j.parco.2008.12.010
M3 - Article
AN - SCOPUS:60649099576
SN - 0167-8191
VL - 35
SP - 138
EP - 150
JO - Parallel Computing
JF - Parallel Computing
IS - 3
ER -