On test generation for combinational circuits consisting of AND and EXOR gates

S. Toida; N. S.V. Rao

doi:10.1109/VTEST.1992.232734

On test generation for combinational circuits consisting of AND and EXOR gates

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Single output logic circuits composed of AND and EXOR gates are studied. It is shown that for two level single output logic circuits composed of AND and EXOR gates, tests that detect all detectable stuck-at faults can be generated in polynomial time. In this method no extra input variables nor extra circuits are required. This contrasts with the fact that for AND, OR circuits the test generation problem is not polynomial time solvable even for two level circuits. Since AND-EXOR circuits can represent any switching function, this suggests that these circuits might be easier to test than AND, OR circuits.

Original language	English
Title of host publication	Digest of Papers - 1992 IEEE VLSI Test Symposium, VLSI 1992
Publisher	IEEE Computer Society
Pages	113-118
Number of pages	6
ISBN (Electronic)	0780306236
DOIs	https://doi.org/10.1109/VTEST.1992.232734
State	Published - 1992
Externally published	Yes
Event	1992 IEEE VLSI Test Symposium, VLSI 1992 - Atlantic City, United States Duration: Apr 7 1992 → Apr 9 1992

Publication series

Name	Proceedings of the IEEE VLSI Test Symposium
Volume	1992-April

Conference

Conference	1992 IEEE VLSI Test Symposium, VLSI 1992
Country/Territory	United States
City	Atlantic City
Period	04/7/92 → 04/9/92

Access to Document

10.1109/VTEST.1992.232734

Cite this

@inproceedings{1322c2f622b343c5a786b3ec5309a59c,

title = "On test generation for combinational circuits consisting of AND and EXOR gates",

abstract = "Single output logic circuits composed of AND and EXOR gates are studied. It is shown that for two level single output logic circuits composed of AND and EXOR gates, tests that detect all detectable stuck-at faults can be generated in polynomial time. In this method no extra input variables nor extra circuits are required. This contrasts with the fact that for AND, OR circuits the test generation problem is not polynomial time solvable even for two level circuits. Since AND-EXOR circuits can represent any switching function, this suggests that these circuits might be easier to test than AND, OR circuits.",

author = "S. Toida and Rao, {N. S.V.}",

note = "Publisher Copyright: {\textcopyright} 1992 IEEE.; 1992 IEEE VLSI Test Symposium, VLSI 1992 ; Conference date: 07-04-1992 Through 09-04-1992",

year = "1992",

doi = "10.1109/VTEST.1992.232734",

language = "English",

series = "Proceedings of the IEEE VLSI Test Symposium",

publisher = "IEEE Computer Society",

pages = "113--118",

booktitle = "Digest of Papers - 1992 IEEE VLSI Test Symposium, VLSI 1992",

}

Toida, S & Rao, NSV 1992, On test generation for combinational circuits consisting of AND and EXOR gates. in Digest of Papers - 1992 IEEE VLSI Test Symposium, VLSI 1992., 232734, Proceedings of the IEEE VLSI Test Symposium, vol. 1992-April, IEEE Computer Society, pp. 113-118, 1992 IEEE VLSI Test Symposium, VLSI 1992, Atlantic City, United States, 04/7/92. https://doi.org/10.1109/VTEST.1992.232734

On test generation for combinational circuits consisting of AND and EXOR gates. / Toida, S.; Rao, N. S.V.
Digest of Papers - 1992 IEEE VLSI Test Symposium, VLSI 1992. IEEE Computer Society, 1992. p. 113-118 232734 (Proceedings of the IEEE VLSI Test Symposium; Vol. 1992-April).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - Single output logic circuits composed of AND and EXOR gates are studied. It is shown that for two level single output logic circuits composed of AND and EXOR gates, tests that detect all detectable stuck-at faults can be generated in polynomial time. In this method no extra input variables nor extra circuits are required. This contrasts with the fact that for AND, OR circuits the test generation problem is not polynomial time solvable even for two level circuits. Since AND-EXOR circuits can represent any switching function, this suggests that these circuits might be easier to test than AND, OR circuits.

AB - Single output logic circuits composed of AND and EXOR gates are studied. It is shown that for two level single output logic circuits composed of AND and EXOR gates, tests that detect all detectable stuck-at faults can be generated in polynomial time. In this method no extra input variables nor extra circuits are required. This contrasts with the fact that for AND, OR circuits the test generation problem is not polynomial time solvable even for two level circuits. Since AND-EXOR circuits can represent any switching function, this suggests that these circuits might be easier to test than AND, OR circuits.

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ER -

On test generation for combinational circuits consisting of AND and EXOR gates

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