Abstract
A custom CMOS analog to digital converter was designed and a prototype 8-channel ADC ASIC was fabricated in a 1.2 μm process. The circuit uses a Wilkinson-type architecture which is suitable for use in multi-channel applications such as the PHENIX detector. The ADC design features include a differential positive-ECL input for the high speed clock and selectable control for 11 or 12-bit conversions making it suitable for use in multiple PHENIX subsystems. Circuit topologies and ASIC layout specifics, including power consumption, maximum clock speed, INL, and DNL are discussed. The ADC performed to 11-bit accuracy.
Original language | English |
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Pages | 417-420 |
Number of pages | 4 |
State | Published - 1996 |
Event | Proceedings of the 1996 IEEE Nuclear Science Symposium. Part 1 (of 3) - Anaheim, CA, USA Duration: Nov 2 1996 → Nov 9 1996 |
Conference
Conference | Proceedings of the 1996 IEEE Nuclear Science Symposium. Part 1 (of 3) |
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City | Anaheim, CA, USA |
Period | 11/2/96 → 11/9/96 |