Multi-channel ADC for use in the PHENIX detector

M. S. Emery, S. S. Frank, C. L. Britton, A. L. Wintenberg, M. L. Simpson, M. N. Ericson, G. R. Young, L. G. Clonts, M. D. Allen

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations

Abstract

A custom CMOS analog to digital converter was designed and a prototype 8-channel ADC ASIC was fabricated in a 1.2 μm process. The circuit uses a Wilkinson-type architecture which is suitable for use in multi-channel applications such as the PHENIX detector. The ADC design features include a differential positive-ECL input for the high speed clock and selectable control for 11 or 12-bit conversions making it suitable for use in multiple PHENIX subsystems. Circuit topologies and ASIC layout specifics, including power consumption, maximum clock speed, INL, and DNL are discussed. The ADC performed to 11-bit accuracy.

Original languageEnglish
Pages417-420
Number of pages4
StatePublished - 1996
EventProceedings of the 1996 IEEE Nuclear Science Symposium. Part 1 (of 3) - Anaheim, CA, USA
Duration: Nov 2 1996Nov 9 1996

Conference

ConferenceProceedings of the 1996 IEEE Nuclear Science Symposium. Part 1 (of 3)
CityAnaheim, CA, USA
Period11/2/9611/9/96

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