Abstract
The use of sintered-silver for large-Area interconnection is attractive for some large-Area bonding applications in power electronics such as the bonding of metal-clad, electrically-insulating substrates to heat sinks. Arrays of different pad sizes and pad shapes have been considered for such large area bonding; however, rather than arbitrarily choosing their size, it is desirable to use the largest size possible where the onset of interconnect delamination does not occur. If that is achieved, then sintered-silver's high thermal and electrical conductivities can be fully taken advantage of. Toward achieving this, a simple and inexpensive proof test is described to identify the largest achievable interconnect size with sinterable silver. The method's objective is to purposely initiate failure or delamination. Copper and invar (a ferrous-nickel alloy whose coefficient of thermal expansion (CTE) is similar to that of silicon or silicon carbide) disks were used in this study and sinterable silver was used to bond them. As a consequence of the method's execution, delamination occurred in some samples during cooling from the 250°C sintering temperature to room temperature and bonding temperature and from thermal cycling in others. These occurrences and their interpretations highlight the method's utility, and the herein described results are used to speculate how sintered-silver bonding will work with other material combinations.
Original language | English |
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State | Published - 2016 |
Event | IMAPS International Conference and Exhibition on High Temperature Electronics, HiTEC 2016 - Albuquerque, United States Duration: May 10 2016 → May 12 2016 |
Conference
Conference | IMAPS International Conference and Exhibition on High Temperature Electronics, HiTEC 2016 |
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Country/Territory | United States |
City | Albuquerque |
Period | 05/10/16 → 05/12/16 |
Keywords
- Coefficient of thermal expansion
- Interconnection
- Residual stress
- Silver
- Sintering