Abstract
Various servers with different characteristics and architectures are hitting the market, and their evaluation and comparison in terms of HPC features is complex and multidimensional. In this paper, we share our experience of evaluating a diverse set of HPC systems, consisting of three mainstream and five emerging architectures. We evaluate the performance and power efficiency using prominent HPC benchmarks, High-Performance Linpack (HPL) and High Performance Conjugate Gradients (HPCG), and expand our analysis using publicly available specialized kernel benchmarks, targeting specific system components. In addition to a large body of quantitative results, we emphasize six usually overlooked aspects of the HPC platforms evaluation, and share our conclusions and lessons learned. Overall, we believe that this paper will improve the evaluation and comparison of HPC platforms, making a first step towards a more reliable and uniform methodology.
| Original language | English |
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| Title of host publication | Proceedings - 2018 30th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2018 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 250-257 |
| Number of pages | 8 |
| ISBN (Electronic) | 9781538677698 |
| DOIs | |
| State | Published - Jul 2 2018 |
| Externally published | Yes |
| Event | 30th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2018 - Lyon, France Duration: Sep 24 2018 → Sep 27 2018 |
Publication series
| Name | Proceedings - 2018 30th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2018 |
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Conference
| Conference | 30th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2018 |
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| Country/Territory | France |
| City | Lyon |
| Period | 09/24/18 → 09/27/18 |
Funding
ACKNOWLEDGEMENT This work was supported by the Spanish Ministry of Science and Technology (project TIN2015-65316-P), Generalitat de Catalunya (contracts 2014-SGR-1051 and 2014-SGR-1272), Severo Ochoa Programme (SEV-2015-0493) of the Spanish Government; and the European Union’s Horizon 2020 research and innovation programme under ExaNoDe project (grant agreement No 671578).
Keywords
- BytelFLOP ratio
- HPC
- emerging and mainstream architectures
- energy efficiency
- memory latency and bandwidth
- weak vs. strong cores