Low dead time variable CMOS delay for the nuclear weapons identification system

B. S. Puckett; M. J. Paulus; J. T. Mihalczo; T. V. Blalock

Low dead time variable CMOS delay for the nuclear weapons identification system

B. S. Puckett, M. J. Paulus, J. T. Mihalczo, T. V. Blalock

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Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

The architecture and performance of a new CMOS, low dead time, variable delay is described. This delay was developed to provide channel synchronization in the front-end electronics ASIC of the Nuclear Weapons Identification System (NWIS). The delay is variable over a 500ns range in steps of less than 100ps. Low dead time is achieved by using a switched parallel channel architecture. The delay channels are feedback stabilized by using a Phase Locked Loop (PLL) with a crystal reference. A prototype has been fabricated in the 1.2u AMI process.

Original language	English
Title of host publication	IEEE Nuclear Science Symposium and Medical Imaging Conference
Publisher	IEEE
Pages	468-472
Number of pages	5
ISBN (Print)	0780350227
State	Published - 1999
Event	Proceedings of the 1998 IEEE Nuclear Science Symposium Conference Record - Toronto, Que, Can Duration: Nov 8 1998 → Nov 14 1998

Publication series

Name	IEEE Nuclear Science Symposium and Medical Imaging Conference
Volume	1

Conference

Conference	Proceedings of the 1998 IEEE Nuclear Science Symposium Conference Record
City	Toronto, Que, Can
Period	11/8/98 → 11/14/98

Cite this

@inproceedings{7aa3fada652b4f8ea10680425e3a7e47,

title = "Low dead time variable CMOS delay for the nuclear weapons identification system",

abstract = "The architecture and performance of a new CMOS, low dead time, variable delay is described. This delay was developed to provide channel synchronization in the front-end electronics ASIC of the Nuclear Weapons Identification System (NWIS). The delay is variable over a 500ns range in steps of less than 100ps. Low dead time is achieved by using a switched parallel channel architecture. The delay channels are feedback stabilized by using a Phase Locked Loop (PLL) with a crystal reference. A prototype has been fabricated in the 1.2u AMI process.",

author = "Puckett, {B. S.} and Paulus, {M. J.} and Mihalczo, {J. T.} and Blalock, {T. V.}",

year = "1999",

language = "English",

isbn = "0780350227",

series = "IEEE Nuclear Science Symposium and Medical Imaging Conference",

publisher = "IEEE",

pages = "468--472",

booktitle = "IEEE Nuclear Science Symposium and Medical Imaging Conference",

note = "Proceedings of the 1998 IEEE Nuclear Science Symposium Conference Record ; Conference date: 08-11-1998 Through 14-11-1998",

}

Puckett, BS, Paulus, MJ, Mihalczo, JT & Blalock, TV 1999, Low dead time variable CMOS delay for the nuclear weapons identification system. in IEEE Nuclear Science Symposium and Medical Imaging Conference. IEEE Nuclear Science Symposium and Medical Imaging Conference, vol. 1, IEEE, pp. 468-472, Proceedings of the 1998 IEEE Nuclear Science Symposium Conference Record, Toronto, Que, Can, 11/8/98.

Low dead time variable CMOS delay for the nuclear weapons identification system. / Puckett, B. S.; Paulus, M. J.; Mihalczo, J. T. et al.
IEEE Nuclear Science Symposium and Medical Imaging Conference. IEEE, 1999. p. 468-472 (IEEE Nuclear Science Symposium and Medical Imaging Conference; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Low dead time variable CMOS delay for the nuclear weapons identification system

AU - Puckett, B. S.

AU - Paulus, M. J.

AU - Mihalczo, J. T.

AU - Blalock, T. V.

PY - 1999

Y1 - 1999

N2 - The architecture and performance of a new CMOS, low dead time, variable delay is described. This delay was developed to provide channel synchronization in the front-end electronics ASIC of the Nuclear Weapons Identification System (NWIS). The delay is variable over a 500ns range in steps of less than 100ps. Low dead time is achieved by using a switched parallel channel architecture. The delay channels are feedback stabilized by using a Phase Locked Loop (PLL) with a crystal reference. A prototype has been fabricated in the 1.2u AMI process.

AB - The architecture and performance of a new CMOS, low dead time, variable delay is described. This delay was developed to provide channel synchronization in the front-end electronics ASIC of the Nuclear Weapons Identification System (NWIS). The delay is variable over a 500ns range in steps of less than 100ps. Low dead time is achieved by using a switched parallel channel architecture. The delay channels are feedback stabilized by using a Phase Locked Loop (PLL) with a crystal reference. A prototype has been fabricated in the 1.2u AMI process.

UR - http://www.scopus.com/inward/record.url?scp=0032597175&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0032597175

SN - 0780350227

T3 - IEEE Nuclear Science Symposium and Medical Imaging Conference

SP - 468

EP - 472

BT - IEEE Nuclear Science Symposium and Medical Imaging Conference

PB - IEEE

T2 - Proceedings of the 1998 IEEE Nuclear Science Symposium Conference Record

Y2 - 8 November 1998 through 14 November 1998

ER -

Low dead time variable CMOS delay for the nuclear weapons identification system

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