TY - GEN
T1 - Light Weight and Fast Simulation Methodology in SystemC for TLM based Behavior Modeling of Programmable Processors
AU - Shashidhar, Saurabh Kumar
AU - Miniskar, Narasinga Rao
AU - Batchu, Sudheer Kumar
AU - Kim, Kyounghoon
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/7
Y1 - 2019/7
N2 - Behavior model of processor cores helps in the performance evaluation of applications and design space exploration of processor architectures such as DSPs, AI processors, etc. even before they are taped out. SystemC is a widely used modeling language to model such processor architectures. High simulation speed of these models are essential for fast evaluation of architectures with application benchmarking and also to meet time-to-market of processor design. However, the traditional SystemC based processes such as SC-CTHREAD, SC-THREAD, and SC-METHOD are limiting the simulation speed due to their frequent context switches, complex event handling and generic nature to cater all types of simulation requirements of EDA industry. In this paper, we propose a novel simulation methodology in SystemC with a new process SC-LIGHT-PROCESS and an ultra light weight simulation engine to achieve 2.6x to >7.9x simulation speed compared to recent SystemC modeling methodologies. Our approach is best suited for easy behavioral modeling of processor architectures in SystemC and requires neither event queues nor complex scheduler. It has been evaluated with behavioral modeling of Audio/Video DSP Reconfigurable Processor system for wide range of audio/video applications.
AB - Behavior model of processor cores helps in the performance evaluation of applications and design space exploration of processor architectures such as DSPs, AI processors, etc. even before they are taped out. SystemC is a widely used modeling language to model such processor architectures. High simulation speed of these models are essential for fast evaluation of architectures with application benchmarking and also to meet time-to-market of processor design. However, the traditional SystemC based processes such as SC-CTHREAD, SC-THREAD, and SC-METHOD are limiting the simulation speed due to their frequent context switches, complex event handling and generic nature to cater all types of simulation requirements of EDA industry. In this paper, we propose a novel simulation methodology in SystemC with a new process SC-LIGHT-PROCESS and an ultra light weight simulation engine to achieve 2.6x to >7.9x simulation speed compared to recent SystemC modeling methodologies. Our approach is best suited for easy behavioral modeling of processor architectures in SystemC and requires neither event queues nor complex scheduler. It has been evaluated with behavioral modeling of Audio/Video DSP Reconfigurable Processor system for wide range of audio/video applications.
KW - Behavioral modeling
KW - Reconfigurable processor
KW - Simulation speed
KW - SystemC
UR - http://www.scopus.com/inward/record.url?scp=85081996603&partnerID=8YFLogxK
U2 - 10.1109/CONECCT47791.2019.9012935
DO - 10.1109/CONECCT47791.2019.9012935
M3 - Conference contribution
AN - SCOPUS:85081996603
T3 - 2019 IEEE International Conference on Electronics, Computing and Communication Technologies, CONECCT 2019
BT - 2019 IEEE International Conference on Electronics, Computing and Communication Technologies, CONECCT 2019
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2019 IEEE International Conference on Electronics, Computing and Communication Technologies, CONECCT 2019
Y2 - 26 July 2019 through 27 July 2019
ER -