Lattice QCD with Domain Decomposition on Intel® Xeon Phi™ Co-Processors

Simon Heybrock; Balint Joó; Dhiraj D. Kalamkar; Mikhail Smelyanskiy; Karthikeyan Vaidyanathan; Tilo Wettig; Pradeep Dubey

doi:10.1109/SC.2014.11

Lattice QCD with Domain Decomposition on Intel® Xeon Phi™ Co-Processors

Simon Heybrock, Balint Joó, Dhiraj D. Kalamkar, Mikhail Smelyanskiy, Karthikeyan Vaidyanathan, Tilo Wettig, Pradeep Dubey

Research output: Contribution to journal › Conference article › peer-review

31 Scopus citations

Abstract

The gap between the cost of moving data and the cost of computing continues to grow, making it ever harder to design iterative solvers on extreme-scale architectures. This problem can be alleviated by alternative algorithms that reduce the amount of data movement. We investigate this in the context of Lattice Quantum Chromo dynamics and implement such an alternative solver algorithm, based on domain decomposition, on Intel® Xeon Phi™ co-processor (KNC) clusters. We demonstrate close-to-linear on-chip scaling to all 60 cores of the KNC. With a mix of single- and half-precision the domain-decomposition method sustains 400-500 Gflop/s per chip. Compared to an optimized KNC implementation of a standard solver [1], our full multi-node domain-decomposition solver strong-scales to more nodes and reduces the time-to-solution by a factor of 5.

Original language	English
Article number	7012993
Pages (from-to)	69-80
Number of pages	12
Journal	International Conference for High Performance Computing, Networking, Storage and Analysis, SC
Volume	2015-January
Issue number	January
DOIs	https://doi.org/10.1109/SC.2014.11
State	Published - Jan 16 2014
Externally published	Yes
Event	International Conference for High Performance Computing, Networking, Storage and Analysis, SC 2014 - New Orleans, United States Duration: Nov 16 2014 → Nov 21 2014

Funding

Funders	Funder number
Deutsche Forschungsgemeinschaft	SFB/TR 55
Directorate for Computer and Information Science and Engineering	1238993

Keywords

Domain decomposition
Intel® Xeon Phi™ coprocessor
Lattice QCD

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10.1109/SC.2014.11

Cite this

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abstract = "The gap between the cost of moving data and the cost of computing continues to grow, making it ever harder to design iterative solvers on extreme-scale architectures. This problem can be alleviated by alternative algorithms that reduce the amount of data movement. We investigate this in the context of Lattice Quantum Chromo dynamics and implement such an alternative solver algorithm, based on domain decomposition, on Intel{\textregistered} Xeon Phi{\texttrademark} co-processor (KNC) clusters. We demonstrate close-to-linear on-chip scaling to all 60 cores of the KNC. With a mix of single- and half-precision the domain-decomposition method sustains 400-500 Gflop/s per chip. Compared to an optimized KNC implementation of a standard solver [1], our full multi-node domain-decomposition solver strong-scales to more nodes and reduces the time-to-solution by a factor of 5.",

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Lattice QCD with Domain Decomposition on Intel® Xeon Phi™ Co-Processors. / Heybrock, Simon; Joó, Balint; Kalamkar, Dhiraj D. et al.
In: International Conference for High Performance Computing, Networking, Storage and Analysis, SC, Vol. 2015-January, No. January, 7012993, 16.01.2014, p. 69-80.

Research output: Contribution to journal › Conference article › peer-review

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AU - Heybrock, Simon

AU - Joó, Balint

AU - Kalamkar, Dhiraj D.

AU - Smelyanskiy, Mikhail

AU - Vaidyanathan, Karthikeyan

AU - Wettig, Tilo

AU - Dubey, Pradeep

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AB - The gap between the cost of moving data and the cost of computing continues to grow, making it ever harder to design iterative solvers on extreme-scale architectures. This problem can be alleviated by alternative algorithms that reduce the amount of data movement. We investigate this in the context of Lattice Quantum Chromo dynamics and implement such an alternative solver algorithm, based on domain decomposition, on Intel® Xeon Phi™ co-processor (KNC) clusters. We demonstrate close-to-linear on-chip scaling to all 60 cores of the KNC. With a mix of single- and half-precision the domain-decomposition method sustains 400-500 Gflop/s per chip. Compared to an optimized KNC implementation of a standard solver [1], our full multi-node domain-decomposition solver strong-scales to more nodes and reduces the time-to-solution by a factor of 5.

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Lattice QCD with Domain Decomposition on Intel® Xeon Phi™ Co-Processors

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