Abstract
Use of non-volatile memory (NVM) devices such as resistive RAM (ReRAM) and spin transfer torque RAM (STT-RAM) for designing on-chip caches holds the promise of providing a high-density, low-leakage alternative to SRAM. However, low write endurance of NVMs, along with the write-variation introduced by existing cache management schemes significantly limits the lifetime of NVM caches. We present LastingNVCache, a technique for improving the cache lifetime by mitigating the intra-set write variation. LastingNVCache works on the key idea that by periodically flushing a frequently-written data-item, next time the block can be made to load into a cold block in the set. Through this, the future writes to that data-item can be redirected from a hot block to a cold block, which leads to improvement in the cache lifetime. Microarchitectural simulations have shown that LastingNVCache provides 6.36X, 9.79X, and 10.94X improvement in lifetime for single, dual and quad-core systems, respectively. Also, its implementation overhead is small and it outperforms a recently proposed technique for improving lifetime of NVM caches.
Original language | English |
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Title of host publication | Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI |
Publisher | IEEE Computer Society |
Pages | 534-540 |
Number of pages | 7 |
ISBN (Electronic) | 9781479937639 |
DOIs | |
State | Published - Sep 18 2014 |
Event | 2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014 - Tampa, United States Duration: Jul 9 2014 → Jul 11 2014 |
Conference
Conference | 2014 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014 |
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Country/Territory | United States |
City | Tampa |
Period | 07/9/14 → 07/11/14 |
Keywords
- Non-volatile memory (NVM)
- device lifetime
- intra-set write variation
- microarchitectural technique
- wear-leveling
- write-endurance