TY - GEN
T1 - Investigation of the via fill process for high density multilayer LTCC substrates
AU - Rowden, Brian
AU - Wang, Gangqiang
AU - Barlow, Fred
AU - Elshabini, Aicha
AU - Zawicki, Larry
AU - Barrier, Gregg
AU - Duncan, Brent
AU - Krueger, Dan
AU - Lopez, Cristie
PY - 2006
Y1 - 2006
N2 - High density electronic packaging for compact and multifunctional electronics demands micro rias for the vertical interconnects in multilayer substrates. With the capabilities of micro rias, fine lines, and large number of layers, low temperature cofired ceramic (LTCC) substrates have recently found wide applications in many industries such as automotive and wireless communication. However, filing micro vias down to 50 um in diameter with conductor ink presents challenges. Lnvestigation of the via fill process indicated that gold based via pastes presented increased difficulty in the injection via fill process as compared to the silver paste counterparts. A significant improvement in continuity related defects was observed with the 75 jam via geometries as compared to the 50 jam geometries for both silver and gold ink systems. The alignment error of via stacks among the printed layers appears to be less than 25 um, though misalignment on the order of 30 to 50 um was noted between the imprinted and printed layers.
AB - High density electronic packaging for compact and multifunctional electronics demands micro rias for the vertical interconnects in multilayer substrates. With the capabilities of micro rias, fine lines, and large number of layers, low temperature cofired ceramic (LTCC) substrates have recently found wide applications in many industries such as automotive and wireless communication. However, filing micro vias down to 50 um in diameter with conductor ink presents challenges. Lnvestigation of the via fill process indicated that gold based via pastes presented increased difficulty in the injection via fill process as compared to the silver paste counterparts. A significant improvement in continuity related defects was observed with the 75 jam via geometries as compared to the 50 jam geometries for both silver and gold ink systems. The alignment error of via stacks among the printed layers appears to be less than 25 um, though misalignment on the order of 30 to 50 um was noted between the imprinted and printed layers.
KW - And high density electronic packaging
KW - Low temperature cofired ceramics (LTCC)
KW - Micro vias
KW - Via formation
UR - http://www.scopus.com/inward/record.url?scp=84876519915&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:84876519915
SN - 0930815807
SN - 9780930815806
T3 - Proceedings - 2006 International Symposium on Microelectronics, IMAPS 2006
SP - 926
EP - 931
BT - Proceedings - 2006 International Symposium on Microelectronics, IMAPS 2006
T2 - 39th International Symposium on Microelectronics, IMAPS 2006
Y2 - 8 October 2006 through 12 October 2006
ER -