Integrated device and process technology for sub-70nm low power DRAM

Changhyun Cho; Sangho Song; Sangho Kim; Sungho Jang; Seongsam Lee; Hyungtak Kim; Junwoong Park; Junshik Bae; Yongsuk Ahn; Yungi Kim; Kinam Kim

Integrated device and process technology for sub-70nm low power DRAM

Changhyun Cho, Sangho Song, Sangho Kim, Sungho Jang, Seongsam Lee, Hyungtak Kim, Junwoong Park, Junshik Bae, Yongsuk Ahn, Yungi Kim, Kinam Kim

Research output: Contribution to journal › Conference article › peer-review

5 Scopus citations

Abstract

A novel process technology for 70nm DRAM was for the first time developed. ArF lithography with lithography friendly layout and highly selective etching process were used for patterning of critical layers. A novel gap-fill technology using spin coating oxide was used for STI and ILD processes. Metal tungsten on dual poly gate and dual gate oxide with plasma nitridation process was used for the performance of peripheral transistors. Bar type bit line contact was used to increase the transistor current about 10%. MIM cell capacitor was developed with buried-OCS scheme and 15Å equivalent Tox and 1fA leakage was confirmed.

Original language	English
Pages (from-to)	32-33
Number of pages	2
Journal	Digest of Technical Papers - Symposium on VLSI Technology
State	Published - 2004
Externally published	Yes
Event	2004 Symposium on VLSI Technology - Digest of Technical Papers - Honolulu, HI, United States Duration: Jun 15 2004 → Jun 17 2004

Cite this

@article{e12217a880564a48982a66e68400480e,

title = "Integrated device and process technology for sub-70nm low power DRAM",

abstract = "A novel process technology for 70nm DRAM was for the first time developed. ArF lithography with lithography friendly layout and highly selective etching process were used for patterning of critical layers. A novel gap-fill technology using spin coating oxide was used for STI and ILD processes. Metal tungsten on dual poly gate and dual gate oxide with plasma nitridation process was used for the performance of peripheral transistors. Bar type bit line contact was used to increase the transistor current about 10%. MIM cell capacitor was developed with buried-OCS scheme and 15{\AA} equivalent Tox and 1fA leakage was confirmed.",

author = "Changhyun Cho and Sangho Song and Sangho Kim and Sungho Jang and Seongsam Lee and Hyungtak Kim and Junwoong Park and Junshik Bae and Yongsuk Ahn and Yungi Kim and Kinam Kim",

year = "2004",

language = "English",

pages = "32--33",

journal = "Digest of Technical Papers - Symposium on VLSI Technology",

issn = "0743-1562",

note = "2004 Symposium on VLSI Technology - Digest of Technical Papers ; Conference date: 15-06-2004 Through 17-06-2004",

}

TY - JOUR

T1 - Integrated device and process technology for sub-70nm low power DRAM

AU - Cho, Changhyun

AU - Song, Sangho

AU - Kim, Sangho

AU - Jang, Sungho

AU - Lee, Seongsam

AU - Kim, Hyungtak

AU - Park, Junwoong

AU - Bae, Junshik

AU - Ahn, Yongsuk

AU - Kim, Yungi

AU - Kim, Kinam

PY - 2004

Y1 - 2004

N2 - A novel process technology for 70nm DRAM was for the first time developed. ArF lithography with lithography friendly layout and highly selective etching process were used for patterning of critical layers. A novel gap-fill technology using spin coating oxide was used for STI and ILD processes. Metal tungsten on dual poly gate and dual gate oxide with plasma nitridation process was used for the performance of peripheral transistors. Bar type bit line contact was used to increase the transistor current about 10%. MIM cell capacitor was developed with buried-OCS scheme and 15Å equivalent Tox and 1fA leakage was confirmed.

AB - A novel process technology for 70nm DRAM was for the first time developed. ArF lithography with lithography friendly layout and highly selective etching process were used for patterning of critical layers. A novel gap-fill technology using spin coating oxide was used for STI and ILD processes. Metal tungsten on dual poly gate and dual gate oxide with plasma nitridation process was used for the performance of peripheral transistors. Bar type bit line contact was used to increase the transistor current about 10%. MIM cell capacitor was developed with buried-OCS scheme and 15Å equivalent Tox and 1fA leakage was confirmed.

UR - http://www.scopus.com/inward/record.url?scp=4544259175&partnerID=8YFLogxK

M3 - Conference article

AN - SCOPUS:4544259175

SN - 0743-1562

SP - 32

EP - 33

JO - Digest of Technical Papers - Symposium on VLSI Technology

JF - Digest of Technical Papers - Symposium on VLSI Technology

T2 - 2004 Symposium on VLSI Technology - Digest of Technical Papers

Y2 - 15 June 2004 through 17 June 2004

ER -

Integrated device and process technology for sub-70nm low power DRAM

Abstract

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