Integrated applications of inspection data in the semiconductor manufacturing environment

As integrated circuit fabrication processes continue to increase in complexity, it has been determined that data collection, retention, and retrieval rates will continue to increase at an alarming rate. At future technology nodes, the time required to source manufacturing problems must at least remain constant to maintain anticipated productivity as suggested in the International Technology Roadmap for Semiconductors (ITRS). Strategies and software methods for integrated yield management have been identified as critical for maintaining this productivity. Integrated yield management must use circuit design, visible defect, parametric, and functional test data to recognize process trends and excursions so that yield-detracting mechanisms can be rapidly identified and corrected. This will require the intelligent merging of the various data sources that are collected and maintained throughout the fabrication environment. The availability of multiple data sources and the evolution of automated analysis techniques are providing mechanisms to convert basic defect, parametric, and electrical data into useful prediction and control information. Oak Ridge National Laboratory and International SEMATECH have been working to develop new strategies and capabilities in integrated yield management based on technologies such as Automatic Defect Classification (ADC), Spatial Signature Analysis (SSA), and Automated Image Retrieval (AIR). In this paper we will discuss a survey of these image-based technologies and their application to the ITRS issues that are driving the need for integration and data reduction.