In-depth optimization with the OpenACC-to-FPGA framework on an arria 10 FPGA

Jacob Lambert; Seyong Lee; Jeffrey S. Vetter; Allen Malony

doi:10.1109/IPDPSW50202.2020.00084

In-depth optimization with the OpenACC-to-FPGA framework on an arria 10 FPGA

Jacob Lambert, Seyong Lee, Jeffrey S. Vetter, Allen Malony

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

The reconfigurable computing paradigm that uses field programmable gate arrays (FPGAs) has received renewed interest in the high-performance computing field due to FPGAs' unique combination of performance and energy efficiency. However, difficulties in programming and optimizing FPGAs have prevented them from being widely accepted as general-purpose computing devices. In accelerator-based heterogeneous computing, portability across diverse heterogeneous devices is also an important issue, but the unique architectural features in FPGAs make this difficult to achieve. To address these issues, a directive-based, high-level FPGA programming and optimization framework was previously developed. In this work, developed optimizations were combined holistically using the directive-based approach to show that each individual benchmark requires a unique set of optimizations to maximize performance. The relationships between FPGA resource usages and runtime performance were also explored.

Original language	English
Title of host publication	Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	460-470
Number of pages	11
ISBN (Electronic)	9781728174457
DOIs	https://doi.org/10.1109/IPDPSW50202.2020.00084
State	Published - May 2020
Event	34th IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020 - New Orleans, United States Duration: May 18 2020 → May 22 2020

Publication series

Name	Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020

Conference

Conference	34th IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020
Country/Territory	United States
City	New Orleans
Period	05/18/20 → 05/22/20

Funding

This research was supported in part by the Exascale Computing Project (17-SC-20-SC), a collaborative effort of the US Department of Energy (DOE) Office of Science (OS) and the National Nuclear Security Administration. This material is based upon work supported by the DOE OS Advanced Scientific Computing Research under contract number DE-AC05-00OR22725.The US government retains— and the publisher, by accepting the article for publication, acknowledges that the US government retains—a nonexclusive, paid-up, irrevocable, worldwide license to publish or reproduce the published form of this manuscript, or allow others to do so, for US government purposes. DOE will provide public access to these results of federally sponsored research in accordance with the DOE Public Access Plan (http://energy.gov/downloads/doe-public-access-plan).

Funders	Funder number
US Department of Energy
U.S. Department of Energy
Office of Science
National Nuclear Security Administration
Advanced Scientific Computing Research	DE-AC05-00OR22725

Keywords

Compiler optimization
Directive-based programming
FPGA
OpenACC
OpenARC

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/IPDPSW50202.2020.00084

Cite this

Lambert, J., Lee, S., Vetter, J. S., & Malony, A. (2020). In-depth optimization with the OpenACC-to-FPGA framework on an arria 10 FPGA. In Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020 (pp. 460-470). Article 9150441 (Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IPDPSW50202.2020.00084

Lambert, Jacob ; Lee, Seyong ; Vetter, Jeffrey S. et al. / In-depth optimization with the OpenACC-to-FPGA framework on an arria 10 FPGA. Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020. Institute of Electrical and Electronics Engineers Inc., 2020. pp. 460-470 (Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020).

@inproceedings{35a12d71b6a448429fcb6e5cda15ab45,

title = "In-depth optimization with the OpenACC-to-FPGA framework on an arria 10 FPGA",

abstract = "The reconfigurable computing paradigm that uses field programmable gate arrays (FPGAs) has received renewed interest in the high-performance computing field due to FPGAs' unique combination of performance and energy efficiency. However, difficulties in programming and optimizing FPGAs have prevented them from being widely accepted as general-purpose computing devices. In accelerator-based heterogeneous computing, portability across diverse heterogeneous devices is also an important issue, but the unique architectural features in FPGAs make this difficult to achieve. To address these issues, a directive-based, high-level FPGA programming and optimization framework was previously developed. In this work, developed optimizations were combined holistically using the directive-based approach to show that each individual benchmark requires a unique set of optimizations to maximize performance. The relationships between FPGA resource usages and runtime performance were also explored.",

keywords = "Compiler optimization, Directive-based programming, FPGA, OpenACC, OpenARC",

author = "Jacob Lambert and Seyong Lee and Vetter, {Jeffrey S.} and Allen Malony",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 34th IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020 ; Conference date: 18-05-2020 Through 22-05-2020",

year = "2020",

month = may,

doi = "10.1109/IPDPSW50202.2020.00084",

language = "English",

series = "Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "460--470",

booktitle = "Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020",

}

Lambert, J, Lee, S , Vetter, JS & Malony, A 2020, In-depth optimization with the OpenACC-to-FPGA framework on an arria 10 FPGA. in Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020., 9150441, Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020, Institute of Electrical and Electronics Engineers Inc., pp. 460-470, 34th IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020, New Orleans, United States, 05/18/20. https://doi.org/10.1109/IPDPSW50202.2020.00084

In-depth optimization with the OpenACC-to-FPGA framework on an arria 10 FPGA. / Lambert, Jacob; Lee, Seyong ; Vetter, Jeffrey S. et al.
Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 460-470 9150441 (Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - In-depth optimization with the OpenACC-to-FPGA framework on an arria 10 FPGA

AU - Lambert, Jacob

AU - Lee, Seyong

AU - Vetter, Jeffrey S.

AU - Malony, Allen

PY - 2020/5

Y1 - 2020/5

N2 - The reconfigurable computing paradigm that uses field programmable gate arrays (FPGAs) has received renewed interest in the high-performance computing field due to FPGAs' unique combination of performance and energy efficiency. However, difficulties in programming and optimizing FPGAs have prevented them from being widely accepted as general-purpose computing devices. In accelerator-based heterogeneous computing, portability across diverse heterogeneous devices is also an important issue, but the unique architectural features in FPGAs make this difficult to achieve. To address these issues, a directive-based, high-level FPGA programming and optimization framework was previously developed. In this work, developed optimizations were combined holistically using the directive-based approach to show that each individual benchmark requires a unique set of optimizations to maximize performance. The relationships between FPGA resource usages and runtime performance were also explored.

AB - The reconfigurable computing paradigm that uses field programmable gate arrays (FPGAs) has received renewed interest in the high-performance computing field due to FPGAs' unique combination of performance and energy efficiency. However, difficulties in programming and optimizing FPGAs have prevented them from being widely accepted as general-purpose computing devices. In accelerator-based heterogeneous computing, portability across diverse heterogeneous devices is also an important issue, but the unique architectural features in FPGAs make this difficult to achieve. To address these issues, a directive-based, high-level FPGA programming and optimization framework was previously developed. In this work, developed optimizations were combined holistically using the directive-based approach to show that each individual benchmark requires a unique set of optimizations to maximize performance. The relationships between FPGA resource usages and runtime performance were also explored.

KW - Compiler optimization

KW - Directive-based programming

KW - FPGA

KW - OpenACC

KW - OpenARC

UR - http://www.scopus.com/inward/record.url?scp=85091584803&partnerID=8YFLogxK

U2 - 10.1109/IPDPSW50202.2020.00084

DO - 10.1109/IPDPSW50202.2020.00084

M3 - Conference contribution

AN - SCOPUS:85091584803

T3 - Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020

SP - 460

EP - 470

BT - Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 34th IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020

Y2 - 18 May 2020 through 22 May 2020

ER -

Lambert J, Lee S , Vetter JS, Malony A. In-depth optimization with the OpenACC-to-FPGA framework on an arria 10 FPGA. In Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020. Institute of Electrical and Electronics Engineers Inc. 2020. p. 460-470. 9150441. (Proceedings - 2020 IEEE 34th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2020). doi: 10.1109/IPDPSW50202.2020.00084

In-depth optimization with the OpenACC-to-FPGA framework on an arria 10 FPGA

Abstract

Publication series

Conference

Funding

Keywords

UN SDGs

Access to Document

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