Implications of memory interference for composed hpc applications

Brian Kocoloski; Yuyu Zhou; Bruce Childers; John Lange

doi:10.1145/2818950.2818965

Implications of memory interference for composed hpc applications

Brian Kocoloski, Yuyu Zhou, Bruce Childers, John Lange

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

5 Scopus citations

Abstract

The cost of inter-node I/O and data movement is becoming increasingly prohibitive for large scale High Performance Computing (HPC) applications. This trend is leading to the emergence of composed in situ applications that co-locate multiple components on the same node. However, these components may contend for underlying memory system resources. In this extended research abstract, we present a preliminary evaluation of the impacts of contention for shared resources in the memory hierarchy, including the last level cache (LLC) and DRAM bandwidth. We show that even modest levels of memory contention can have substantial performance implications for some benchmarks, and argue for a cross layer approach to resource partitioning and scheduling on future HPC systems.

Original language	English
Title of host publication	MEMSYS 2015 - Proceedings of the 1st International Symposium on Memory Systems
Publisher	Association for Computing Machinery
Pages	95-97
Number of pages	3
ISBN (Electronic)	9781450336048
DOIs	https://doi.org/10.1145/2818950.2818965
State	Published - Oct 5 2015
Externally published	Yes
Event	1st International Symposium on Memory Systems, MEMSYS 2015 - Washington, United States Duration: Aug 14 2015 → Aug 15 2015

Publication series

Name	ACM International Conference Proceeding Series
Volume	05-08-October-2015

Conference

Conference	1st International Symposium on Memory Systems, MEMSYS 2015
Country/Territory	United States
City	Washington
Period	08/14/15 → 08/15/15

Keywords

Composed applications
High performance computing
Shared memory

Access to Document

10.1145/2818950.2818965

Cite this

Kocoloski, B., Zhou, Y., Childers, B., & Lange, J. (2015). Implications of memory interference for composed hpc applications. In MEMSYS 2015 - Proceedings of the 1st International Symposium on Memory Systems (pp. 95-97). (ACM International Conference Proceeding Series; Vol. 05-08-October-2015). Association for Computing Machinery. https://doi.org/10.1145/2818950.2818965

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title = "Implications of memory interference for composed hpc applications",

abstract = "The cost of inter-node I/O and data movement is becoming increasingly prohibitive for large scale High Performance Computing (HPC) applications. This trend is leading to the emergence of composed in situ applications that co-locate multiple components on the same node. However, these components may contend for underlying memory system resources. In this extended research abstract, we present a preliminary evaluation of the impacts of contention for shared resources in the memory hierarchy, including the last level cache (LLC) and DRAM bandwidth. We show that even modest levels of memory contention can have substantial performance implications for some benchmarks, and argue for a cross layer approach to resource partitioning and scheduling on future HPC systems.",

keywords = "Composed applications, High performance computing, Shared memory",

author = "Brian Kocoloski and Yuyu Zhou and Bruce Childers and John Lange",

note = "Publisher Copyright: {\textcopyright}2015 Copyright held by the owner/author(s).; 1st International Symposium on Memory Systems, MEMSYS 2015 ; Conference date: 14-08-2015 Through 15-08-2015",

year = "2015",

month = oct,

day = "5",

doi = "10.1145/2818950.2818965",

language = "English",

series = "ACM International Conference Proceeding Series",

publisher = "Association for Computing Machinery",

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Kocoloski, B, Zhou, Y, Childers, B & Lange, J 2015, Implications of memory interference for composed hpc applications. in MEMSYS 2015 - Proceedings of the 1st International Symposium on Memory Systems. ACM International Conference Proceeding Series, vol. 05-08-October-2015, Association for Computing Machinery, pp. 95-97, 1st International Symposium on Memory Systems, MEMSYS 2015, Washington, United States, 08/14/15. https://doi.org/10.1145/2818950.2818965

Implications of memory interference for composed hpc applications. / Kocoloski, Brian; Zhou, Yuyu; Childers, Bruce et al.
MEMSYS 2015 - Proceedings of the 1st International Symposium on Memory Systems. Association for Computing Machinery, 2015. p. 95-97 (ACM International Conference Proceeding Series; Vol. 05-08-October-2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Implications of memory interference for composed hpc applications

AU - Kocoloski, Brian

AU - Zhou, Yuyu

AU - Childers, Bruce

AU - Lange, John

PY - 2015/10/5

Y1 - 2015/10/5

N2 - The cost of inter-node I/O and data movement is becoming increasingly prohibitive for large scale High Performance Computing (HPC) applications. This trend is leading to the emergence of composed in situ applications that co-locate multiple components on the same node. However, these components may contend for underlying memory system resources. In this extended research abstract, we present a preliminary evaluation of the impacts of contention for shared resources in the memory hierarchy, including the last level cache (LLC) and DRAM bandwidth. We show that even modest levels of memory contention can have substantial performance implications for some benchmarks, and argue for a cross layer approach to resource partitioning and scheduling on future HPC systems.

AB - The cost of inter-node I/O and data movement is becoming increasingly prohibitive for large scale High Performance Computing (HPC) applications. This trend is leading to the emergence of composed in situ applications that co-locate multiple components on the same node. However, these components may contend for underlying memory system resources. In this extended research abstract, we present a preliminary evaluation of the impacts of contention for shared resources in the memory hierarchy, including the last level cache (LLC) and DRAM bandwidth. We show that even modest levels of memory contention can have substantial performance implications for some benchmarks, and argue for a cross layer approach to resource partitioning and scheduling on future HPC systems.

KW - Composed applications

KW - High performance computing

KW - Shared memory

UR - https://www.scopus.com/pages/publications/84959374044

U2 - 10.1145/2818950.2818965

DO - 10.1145/2818950.2818965

M3 - Conference contribution

AN - SCOPUS:84959374044

T3 - ACM International Conference Proceeding Series

SP - 95

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BT - MEMSYS 2015 - Proceedings of the 1st International Symposium on Memory Systems

PB - Association for Computing Machinery

T2 - 1st International Symposium on Memory Systems, MEMSYS 2015

Y2 - 14 August 2015 through 15 August 2015

ER -

Implications of memory interference for composed hpc applications

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Keywords

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