Abstract
Aditya-L1, ISRO’s first solar observatory is carrying out the study of sun from L1-Lagrange point with its suite of seven instruments. Visible Emission Line Coronagraph (VELC) is one such instrument, which will provide observations close to solar limb with internal occultation in visible and near infrared (IR) region. This paper provides details of design and development of electronics for continuum, two spectroscopic and spectro- polarimetry channels of VELC instrument. These are realized using sCMOS detectors in visible and two spectroscopic chains respectively. Developed hardware comprises of detector front-end electronics, control and data processing electronics and DC-DC converter electronics. On-board intelligence algorithm is implemented for detection of Coronal Mass Ejection (CME) events. Payload is designed to have ultra-high sensitivity (noise equivalent signal = 0.2 photon/sec/pixel). Dark noise of <1.2e with dark signal ≈0.035e/p/s is achieved. The instrument provide ultra-high sensing dynamic range >120 dB with single photon detection capability and 18-bit radiometric resolution. Imaging with simulated target (with input of 15-photon max.) was carried out. These VELC performances are best among worldwide solar coronagraphs satellite. Control of instrument background is critical to achieve the desired scientific goal. Hence stringent contamination control protocols were evolved and implemented during all stages of payload development. The instrument (all 4-channels) consumes 105W of power, is realized with mass <25kg and output data rate is ≈ 1 Gbps (burst mode, all channels). This paper provide details about design, development, challenges,ground testing and onboard performance of VELC instrument.
Original language | English |
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Pages (from-to) | 53-63 |
Number of pages | 11 |
Journal | Journal of Spacecraft Technology |
Volume | 35 |
Issue number | 1 |
State | Published - 2024 |
Externally published | Yes |
Keywords
- Aditya-L1 mission
- CME
- detector
- electronics
- FPGA
- photon sensing
- sCMOS
- SNR
- VELC