Abstract
Accelerator-enhanced computing platforms have drawn a lot of attention due to their massive peak commutational capacity. Despite significant advances in the progriming interfaces to such hybrid architectures, traditional programming paradigms struggle with mapping the resulting multi-dimensional heterogeneity and the expression of algarhythm parallelism, resulting in sub-optimal effective performance. Task-based programming paradigms have the capability to alleviate some of the programming challenges on distributed hybrid many-core architectures. In this paper we take this concept a step further by showing that the potential of task-based programming paradigms can be greatly increased with minimal modification of the underlying runtime combined with the right algorithmic changes. We propose two novel recursive algorithmic variants for one-sided factorizations and describe the changes to the PaRSEC task-scheduling runtime to build a framework where the task granularity is dynamically adjusted to adapt the degree of available parallelism and kernel efficiency according to runtime conditions. Based on an extensive set of results, we show that, with one-sided factorizations, i.e. Colicky, and QR, a carefully written algorithm, supported by an adaptive tasks-based runtime, is capable of reaching a degree of performance and scalability never achieved before in distributed hybrid environments.
Original language | English |
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Title of host publication | Proceedings - 2015 IEEE 29th International Parallel and Distributed Processing Symposium, IPDPS 2015 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 156-165 |
Number of pages | 10 |
ISBN (Electronic) | 9781479986484 |
DOIs | |
State | Published - Jul 17 2015 |
Event | 29th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2015 - Hyderabad, India Duration: May 25 2015 → May 29 2015 |
Publication series
Name | Proceedings - 2015 IEEE 29th International Parallel and Distributed Processing Symposium, IPDPS 2015 |
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Conference
Conference | 29th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2015 |
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Country/Territory | India |
City | Hyderabad |
Period | 05/25/15 → 05/29/15 |
Funding
This material is based upon work supported by the Department of Energy under Award Number DE-SC0010682, by the National Science Foundation under Grant Number CCF-1244905, in part by the Russian Scientific Fund Agreement N14-11-00190, and by the Inria associated team MORSE.
Keywords
- GPU
- PaRSEC runtime
- dense linear algebra
- heterogeneous architecture