Fully integrated current-mode CMOS gated baseline restorer circuits

James M. Rochelle; David M. Binkley; Michael J. Paulus

Fully integrated current-mode CMOS gated baseline restorer circuits

James M. Rochelle, David M. Binkley, Michael J. Paulus

Research output: Contribution to conference › Paper › peer-review

1 Scopus citations

Abstract

The design and performance results for three different fully-integrated gated baseline restorer (BLR) circuits used in a new PET current-mode front-end CMOS ASIC are presented. The BLR circuits are capable of correcting for count-rate dependent baseline shifts due to detector ac coupling and correct for accumulated CMOS dc offsets in the signal processing channels. Gated integrator input offsets currents are maintained below 50 nA, keeping the gated integrator output error below 10 mV for an 850 ns integrator period. Constant fraction discriminator (CFD) constant fraction comparator input offset is maintained at submillivolt levels, and arming comparator threshold is maintained at a 0-0.48 V level under on-board DAC control.

Original language	English
Pages	39-43
Number of pages	5
State	Published - 1995
Externally published	Yes
Event	Proceedings of the 1994 Nuclear Science Symposium and Medical Imaging Conference. Part 1 (of 4) - Norfolk, VA, USA Duration: Oct 30 1994 → Nov 5 1994

Conference

Conference	Proceedings of the 1994 Nuclear Science Symposium and Medical Imaging Conference. Part 1 (of 4)
City	Norfolk, VA, USA
Period	10/30/94 → 11/5/94

Cite this

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title = "Fully integrated current-mode CMOS gated baseline restorer circuits",

abstract = "The design and performance results for three different fully-integrated gated baseline restorer (BLR) circuits used in a new PET current-mode front-end CMOS ASIC are presented. The BLR circuits are capable of correcting for count-rate dependent baseline shifts due to detector ac coupling and correct for accumulated CMOS dc offsets in the signal processing channels. Gated integrator input offsets currents are maintained below 50 nA, keeping the gated integrator output error below 10 mV for an 850 ns integrator period. Constant fraction discriminator (CFD) constant fraction comparator input offset is maintained at submillivolt levels, and arming comparator threshold is maintained at a 0-0.48 V level under on-board DAC control.",

author = "Rochelle, {James M.} and Binkley, {David M.} and Paulus, {Michael J.}",

year = "1995",

language = "English",

pages = "39--43",

note = "Proceedings of the 1994 Nuclear Science Symposium and Medical Imaging Conference. Part 1 (of 4) ; Conference date: 30-10-1994 Through 05-11-1994",

}

TY - CONF

T1 - Fully integrated current-mode CMOS gated baseline restorer circuits

AU - Rochelle, James M.

AU - Binkley, David M.

AU - Paulus, Michael J.

PY - 1995

Y1 - 1995

N2 - The design and performance results for three different fully-integrated gated baseline restorer (BLR) circuits used in a new PET current-mode front-end CMOS ASIC are presented. The BLR circuits are capable of correcting for count-rate dependent baseline shifts due to detector ac coupling and correct for accumulated CMOS dc offsets in the signal processing channels. Gated integrator input offsets currents are maintained below 50 nA, keeping the gated integrator output error below 10 mV for an 850 ns integrator period. Constant fraction discriminator (CFD) constant fraction comparator input offset is maintained at submillivolt levels, and arming comparator threshold is maintained at a 0-0.48 V level under on-board DAC control.

AB - The design and performance results for three different fully-integrated gated baseline restorer (BLR) circuits used in a new PET current-mode front-end CMOS ASIC are presented. The BLR circuits are capable of correcting for count-rate dependent baseline shifts due to detector ac coupling and correct for accumulated CMOS dc offsets in the signal processing channels. Gated integrator input offsets currents are maintained below 50 nA, keeping the gated integrator output error below 10 mV for an 850 ns integrator period. Constant fraction discriminator (CFD) constant fraction comparator input offset is maintained at submillivolt levels, and arming comparator threshold is maintained at a 0-0.48 V level under on-board DAC control.

UR - http://www.scopus.com/inward/record.url?scp=0029239154&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0029239154

SP - 39

EP - 43

T2 - Proceedings of the 1994 Nuclear Science Symposium and Medical Imaging Conference. Part 1 (of 4)

Y2 - 30 October 1994 through 5 November 1994

ER -

Fully integrated current-mode CMOS gated baseline restorer circuits

Abstract

Conference

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